latency_fifo_inst.vhd

来自「基于altera 芯片得ofdm调制解调源程序」· VHDL 代码 · 共 11 行

latency_fifo_inst : latency_fifo PORT MAP (
		clock	 => clock_sig,
		data	 => data_sig,
		rdreq	 => rdreq_sig,
		sclr	 => sclr_sig,
		wrreq	 => wrreq_sig,
		empty	 => empty_sig,
		full	 => full_sig,
		q	 => q_sig
	);