pcie_blk_plus_release_notes.txt

基于xilinx vierex5得pci express dma设计实现。

	Core Name: Xilinx LogiCORE Endpoint Block Plus for PCI Express(R)
	Version: 1.5 Rev1 EA
	Release Date: October 10, 2007


=======================================================================

This document contains the following sections:

1. Introduction
2. New Features
3. Resolved Issues
4. Known Issues
5. Technical Support
6. Other Information
7. Core Release History

=======================================================================

1. INTRODUCTION

For the most recent updates to the IP installation instructions for this core,
please go to:

   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for version 1.5 of the Xilinx LogiCORE
Endpoint Block Plus for PCI Express solution. For the latest core updates,
please visit the LogiCORE Endpoint Block Plus for PCI Express Lounge. The
lounge is accessible from the "Access Lounge" button on the cores product page:

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=V5_PCI_Express_Block_Plus

For information on how to set up and use the core, please refer to the LogiCORE
Endpoint Block Plus for PCI Express Getting Started Guide.  More comprehensive
user information is available in the LogiCORE Endpoint Block Plus for PCI
Express User Guide.


2. New Features

   - ISE 9.2i software support
   - Added support for up to 32 MSI vectors.
        New ports added to implement feature:
	       input              cfg_interrupt_assert_n,
	       input        [7:0] cfg_interrupt_di,
	       output       [2:0] cfg_interrupt_mmenable,
	       output             cfg_interrupt_msienable,
	       output       [7:0] cfg_interrupt_do,
        For designs upgrading from previous versions, users must modify the
	core instantiation to add these additional ports.


3. Resolved Issues

   - Receive Flow Control Credit Signals
      o CR 434731

      Core Receive Flow Control Credit Available signals:
      trn_rfc_{p,np}h_av[7:0] and trn_rfc_{p,np}d_av[11:0]  now indicate the
      correct values.

   - TS2 link Upconfigure bit causing failure to link train
      o CR 443006

      Problem fixed where setting the Link Upconfigure bit in a TS2 caused the
      Integrated Hard Block for PCI Express to fail to link train.

   - Packets with Phantom Function not being passed to the User Application
      o CR 448355

      Issue resolved where packets using Phantom Functions were being dropped
      by the Block Plus core

   - Recording of Error Status assertions fixed
      o CR 448685

      Issue resolved where assertions of certain Error Status signals were not
      being recorded in certain cases, by the Block Plus core

   - "Advanced Flow Control Options" in GUI not being passed to netlist
      o CR 447613

      The Advanced Flow Control Option GUI choices were not propagated to the 
      core netlist. In addition, the INFINITECOMPLETIONS attribute on the 
      block was always set to FALSE, regardless of the options selected in the 
      GUI. This caused the core to not be compliant. A PCI Express endpoint is 
      required to advertise infinite completion credits. This problem is fixed 
      so that the options selected in the GUI are passed to the netlist, 
      correctly setting the posted and non-posted header credit and 
      INFINITECOMPLETIONS attributes on the built-in block for PCI Express.

   -  Completion Credit Advertised in Non-INFINITECOMPLETIONS Mode Incorrect
      o CR 448357

      The Completion Header and Data Credit advertised in Non-INFINITECOMPLETION
      Mode was incorrect. The core continued to advertise INFINITE Credits, even 
      though INFINITECOMPLETIONS was set to FALSE. This problem is fixed by setting 
      the VC0TOTALCREDITSCH and VC0TOTALCREDITSCD to the correct values when 
      Non-INFINITECOMPLETIONS setting is chosen.

4. Known Issues

    The following are known issues for v1.5 of this core at the time of release.

    4.1  Functional Issues

          - None

    4.2  Implementation Issues

          - Simulation Only Issue : Large Simulation Times
          o CR 448685

            Simulation takes a long time to achieve trn_lnk_up_n assertion.
	    This is because GTP model drives the serial lines to Unknown logic
	    state, when signaling Electrical Idle during the link training phase.
	    Refer to Xilinx Answer 29294 for a work around to this issue.

          - Speed file and design changes

            The design files present in this release are based on timing parameters
            from, and intended for use with, the speed files shipped with ISE 9.1
            SP3. As more device characterization data is collected, Xilinx may
            update the speed files to more closely model device operation.

            Xilinx reserves the right to modify the design files, including the core
            pin-out, in order to maintain full compliance after speed files updates
            occur. To the full extent possible, Xilinx will incorporate such
            modifications without using pin-out changes in an effort to provide
            "transparent" design file updates.

           - Timing Closure

            In order to obtain timing closure, designers may be required to use
            multiple PAR seeds and/or floorplanning. Using Multi-Pass Place and
            Route (MPPR), designers can try multiple cost tables in order to meet
            timing. Please see the Development System Reference Guide in the
            Software Manuals found at: http://www.xilinx.com/support/library.htm for
            more information on using MPPR. Designers may also have to floorplan and
            add advanced placement constraints for both their design and the
            core to meet timing.

            - Xilinx warnings

            The Xilinx tools may issue various warnings, however no errors should
            occur.

5. TECHNICAL SUPPORT

   To obtain technical support, create a WebCase at
   http://www.xilinx.com/support.
   Questions are routed to a team expertise in using this product.

   Xilinx provides technical support for use of this product when used according
   to the guidelines described in the core documentation, and cannot guarantee
   timing, functionality, or support of this product for designs that do not
   follow specified guidelines.


6. OTHER INFORMATION

   - Answer Record

   For the most up to date list of known issues with the core, please refer to
   Answer Record 25222:

   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=25222


7. CORE RELEASE HISTORY

Date     By            Version      Description
===============================================================================
02/2007  Xilinx, Inc.  1.2          9.1i SP2 - IP Update 1
03/2007  Xilinx, Inc.  1.2 rev 1    Update for rev 1 patch
05/2007  Xilinx, Inc.  1.3          9.1i SP3 - IP Update 3
08/2007  Xilinx, Inc.  1.4          9.2i SP2 - IP Update 1
10/2007  Xilinx, Inc.  1.5          9.2i SP3 - IP Update 2
10/2007  Xilinx, Inc.  1.5 EA       Add support for V5 SXT/LXT ES devices
===============================================================================

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