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📁 基于xilinx vierex5得pci express dma设计实现。
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# //  ModelSim SE 6.2e Nov 16 2006 Linux 2.6.9-42.0.3.ELsmp# //# //  Copyright 2006 Mentor Graphics Corporation# //              All Rights Reserved.# //# //  THIS WORK CONTAINS TRADE SECRET AND # //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS# //  AND IS SUBJECT TO LICENSE TERMS.# //do simulate_mti.do# ** Warning: (vlib-34) Library already exists at "work".# Reading modelsim.ini# "work" maps to directory work. (Default mapping)# Model Technology ModelSim SE vlog 6.2e Compiler 2006.11 Nov 16 2006# -- Compiling module novas_vlog# # Top level modules:# 	novas_vlog# Model Technology ModelSim SE vlog 6.2e Compiler 2006.11 Nov 16 2006# -- Compiling module BMD# -- Compiling module BMD_64_RX_ENGINE# -- Compiling module BMD_64_TX_ENGINE# -- Compiling module BMD_EP_MEM_ACCESS# -- Compiling module BMD_EP_MEM# -- Compiling module BMD_EP# -- Compiling module BMD_INTR_CTRL# -- Compiling module BMD_TO_CTRL# -- Compiling module xilinx_pci_exp_1_lane_ep# -- Compiling module pci_exp_64b_app# -- Compiling module endpoint_blk_plus_v1_5# -- Compiling module glbl# -- Compiling module boardx01# -- Compiling module xilinx_pci_exp_1_lane_downstream_port# -- Compiling module xilinx_pci_exp_1_lane_dsport# -- Compiling module dsport_cfg# -- Compiling module pci_exp_usrapp_rx# -- Compiling module pci_exp_usrapp_tx# -- Compiling module pci_exp_usrapp_com# -- Compiling module pci_exp_usrapp_cfg# -- Compiling module pci_exp_1_lane_64b_dsport# -- Compiling module sys_clk_gen# -- Compiling module sys_clk_gen_ds# -- Scanning library directory '/program/ise92/verilog/src/simprims'# -- Scanning library directory '/program/ise92/verilog/src/unisims'# -- Compiling module IBUFDS# -- Compiling module IBUF# -- Compiling module VCC# -- Compiling module GND# -- Compiling module INV# -- Compiling module LUT5# -- Compiling module LUT3# -- Compiling module LUT4# -- Compiling module FDR# -- Compiling module LUT2# -- Compiling module LUT6# -- Compiling module FDC# -- Compiling module FDCE# -- Compiling module FD# -- Compiling module BUFG# -- Compiling module PLL_ADV# -- Compiling module PCIE_INTERNAL_1_1# -- Compiling module RAMB36_EXP# -- Compiling module RAMB36SDP_EXP# -- Compiling module FDRE# -- Compiling module GTP_DUAL# -- Compiling module LDP_1# -- Compiling module FDE# -- Compiling module SRLC16E# -- Compiling module MUXF7# -- Compiling module LUT1# -- Compiling module FDRSE# -- Compiling module FDRS# -- Compiling module FDS# -- Compiling module FDSE# -- Compiling module MUXCY# -- Compiling module XORCY# -- Compiling module RAM32X1D# -- Compiling module FDP# -- Compiling module GT11CLK_MGT# -- Compiling module OBUF# -- Compiling module LUT2_L# -- Compiling module LUT4_L# -- Compiling module LUT1_L# -- Compiling module LUT3_L# -- Compiling module MUXF5# -- Compiling module FDPE# -- Compiling module BUF# -- Compiling module DCM_ADV# -- Compiling module dcm_adv_clock_divide_by_2# -- Compiling module dcm_adv_maximum_period_check# -- Compiling module dcm_adv_clock_lost# -- Compiling module MUXCY_L# -- Compiling module SRLC16# -- Compiling module SRL16# -- Compiling module GT11# -- Compiling module RAM16X1D# -- Compiling module MULT_AND# -- Compiling module SRL16E# -- Compiling module RAMB16_S9_S9# -- Compiling module RAMB16_S18_S18# -- Compiling module MUXF6# -- Compiling module ARAMB36_INTERNAL# -- Scanning library directory '/program/ise92/smartmodel/lin/wrappers/mtiverilog'# -- Compiling module PCIE_INTERNAL_1_1_SWIFT# -- Compiling module GTP_DUAL_SWIFT# -- Compiling module GT11_SWIFT# -- Compiling module PCIE_INTERNAL_1_1_SWIFT_BIT# -- Compiling module GTP_DUAL_SWIFT_BIT# -- Compiling module GT11_SWIFT_BIT# # Top level modules:# 	glbl# 	boardx01# vsim +notimingchecks +TESTNAME=BMD_Rd_n_Wr_DMA -L work -pli libpli.so novas_vlog work.boardx01 glbl # ** Note: (vsim-3813) Design is being optimized due to module recompilation...# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.# Loading /program/modeltech/linux/libswiftpli.sl# Loading ./libpli.so# Loading work.novas_vlog(fast)# Loading work.boardx01(fast)# ** Warning: (vsim-3010) [TSCALE] - Module 'boardx01' has a `timescale directive in effect, but previous modules do not.#         Region: /boardx01# Loading work.xilinx_pci_exp_1_lane_ep(fast)# Loading work.IBUFDS(fast)# Loading work.IBUF(fast)# Loading work.pci_exp_64b_app(fast)# Loading work.BMD(fast)# Loading work.BMD_EP(fast)# Loading work.BMD_EP_MEM_ACCESS(fast)# Loading work.BMD_EP_MEM(fast)# Loading work.BMD_64_RX_ENGINE(fast)# Loading work.BMD_64_TX_ENGINE(fast)# Loading work.BMD_INTR_CTRL(fast)# Loading work.BMD_TO_CTRL(fast)# Loading work.endpoint_blk_plus_v1_5(fast)# Loading work.VCC(fast)# Loading work.GND(fast)# Loading work.INV(fast)# Loading work.LUT5(fast)# Loading work.LUT3(fast)# Loading work.LUT4(fast)# Loading work.FDR(fast)# Loading work.LUT2(fast)# Loading work.LUT6(fast)# Loading work.LUT2(fast__1)# Loading work.LUT2(fast__2)# Loading work.FDC(fast)# Loading work.FDCE(fast)# Loading work.FD(fast)# Loading work.BUFG(fast)# Loading work.PLL_ADV(fast)# Loading work.PCIE_INTERNAL_1_1(fast)# Loading work.PCIE_INTERNAL_1_1_SWIFT(fast)# Loading work.PCIE_INTERNAL_1_1_SWIFT_BIT(fast)# Loading work.RAMB36_EXP(fast)# Loading work.ARAMB36_INTERNAL(fast)# Loading work.RAMB36SDP_EXP(fast)# Loading work.ARAMB36_INTERNAL(fast__1)# Loading work.FDRE(fast)# Loading work.GTP_DUAL(fast)# Loading work.GTP_DUAL_SWIFT(fast)# Loading work.GTP_DUAL_SWIFT_BIT(fast)# Loading work.LDP_1(fast)# Loading work.FD(fast__1)# Loading work.FDE(fast)# Loading work.SRLC16E(fast)# Loading work.MUXF7(fast)# Loading work.LUT2(fast__3)# Loading work.RAMB36SDP_EXP(fast__1)# Loading work.ARAMB36_INTERNAL(fast__2)# Loading work.LUT2(fast__4)# Loading work.LUT2(fast__5)# Loading work.LUT1(fast)# Loading work.FDRSE(fast)# Loading work.FDRS(fast)# Loading work.FDS(fast)# Loading work.LUT2(fast__6)# Loading work.LUT2(fast__7)# Loading work.LUT2(fast__8)# Loading work.FDSE(fast)# Loading work.FDRSE(fast__1)# Loading work.FDE(fast__1)# Loading work.MUXCY(fast)# Loading work.XORCY(fast)# Loading work.FDSE(fast__1)# Loading work.RAM32X1D(fast)# Loading work.FDP(fast)# Loading work.xilinx_pci_exp_1_lane_downstream_port(fast)# Loading work.xilinx_pci_exp_1_lane_dsport(fast)# Loading work.GT11CLK_MGT(fast)# Loading work.OBUF(fast)# Loading work.pci_exp_1_lane_64b_dsport(fast)# Loading work.LUT1(fast__1)# Loading work.LUT2_L(fast)# Loading work.LUT4_L(fast)# Loading work.LUT2_L(fast__1)# Loading work.LUT1_L(fast)# Loading work.LUT2_L(fast__2)# Loading work.LUT2_L(fast__3)# Loading work.LUT3_L(fast)# Loading work.LUT2(fast__9)# Loading work.MUXF5(fast)# Loading work.LUT2_L(fast__4)# Loading work.LUT2_L(fast__5)# Loading work.LUT2_L(fast__6)
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