wave_rx.do

基于xilinx vierex5得pci express dma设计实现。

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rdst_rdy_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rnp_ok_n
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rd
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rrem_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rsof_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_reof_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rsrc_rdy_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rsrc_dsc_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rerrfwd_n
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rbar_hit_n
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rfc_nph_av
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rfc_npd_av
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rfc_ph_av
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rfc_pd_av
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rfc_cplh_av
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rfc_cpld_av
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_clk
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_reset_n
add wave -noupdate -color Orange -format Logic -itemcolor Orange /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_lnk_up_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/next_trn_rdst_rdy_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/next_trn_rnp_ok_n
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rx_state
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/next_trn_rx_state
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rx_in_frame
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/next_trn_rx_in_frame
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rx_in_channel
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/next_trn_rx_in_channel
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/next_trn_rx_timeout
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rdst_rdy_toggle_count
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/trn_rnp_ok_toggle_count
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/rx_usrapp/sim_timeout
add wave -noupdate -divider tx
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_td
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_trem_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_tsof_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_teof_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_terrfwd_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_tsrc_rdy_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_tsrc_dsc_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_clk
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_reset_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_lnk_up_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_tdst_rdy_n
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_tdst_dsc_n
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/trn_tbuf_av
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/i
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/j
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/k
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/ADDRESS_32_L
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/ADDRESS_32_H
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/ADDRESS_64
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/COMPLETER_ID
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/COMPLETER_ID_CFG
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/REQUESTER_ID
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DESTINATION_RID
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEFAULT_TC
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEFAULT_LENGTH
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEFAULT_BE_LAST_DW
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEFAULT_BE_FIRST_DW
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEFAULT_ATTR
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEFAULT_TAG
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEFAULT_COMP
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/EXT_REG_ADDR
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/TD
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/EP
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/VENDOR_ID
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/LENGTH
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/RAND_
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/CFG_DWADDR
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_DEV_BDF
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_IO_ADDR
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_ADDRESS_1L
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_ADDRESS_2L
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_ADDRESS_3L
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_ADDRESS_4L
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_ADDRESS_H
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_CFG_DWADDR
add wave -noupdate -format Event /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/test_begin
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_ADDRESS_MASK
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_READ_DATA
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/data
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/p_read_data_valid
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/P_WRITE_DATA
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/temp_register
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/BAR_INIT_P_MEM64_HI_START
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/BAR_INIT_P_MEM64_LO_START
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/BAR_INIT_P_MEM32_START
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/BAR_INIT_P_IO_START
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/BAR_INIT_TEMP
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/OUT_OF_LO_MEM
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/OUT_OF_IO
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/OUT_OF_HI_MEM
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/ii
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/jj
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/DEV_VEN_ID
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/PIO_MAX_NUM_BLOCK_RAMS
add wave -noupdate -format Literal -radix hexadecimal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/PIO_MAX_MEMORY
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/PIO_ADDRESS
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/pio_check_design
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/cpld_to
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/cpld_to_finish
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/verbose
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/NUMBER_OF_IO_BARS
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/NUMBER_OF_MEM32_BARS
add wave -noupdate -format Literal /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/NUMBER_OF_MEM64_BARS
add wave -noupdate -format Literal -radix ascii /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/testname
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/expect_status
add wave -noupdate -format Logic /boardx01/xilinx_pci_exp_1_lane_downstream_port/tx_usrapp/expect_finish_check
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {81422957 ps} 0}
configure wave -namecolwidth 227
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {79972598 ps} {95890292 ps}