xst.srp

基于xilinx vierex5得pci express dma设计实现。

Optimizing unit <BMD_INTR_CTRL> ...

Optimizing unit <BMD_EP_MEM_ACCESS> ...

Optimizing unit <BMD_64_TX_ENGINE> ...

Optimizing unit <BMD_EP> ...

Optimizing unit <BMD> ...
WARNING:Xst:2677 - Node <BMD_TO/cfg_turnoff_ok_n> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_TO/trn_pending> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_4> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_5> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_6> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_7> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_7> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_8> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_9> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_10> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_4> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_5> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_6> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_7> of sequential type is unconnected in block <app/BMD>.

Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txn<0>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txp<0>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 842
 Flip-Flops                                            : 842

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : xilinx_pci_exp_1_lane_ep.ngc
Output Format                      : NGC
Optimization Goal                  : SPEED
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 7

Cell Usage :
# BELS                             : 1772
#      GND                         : 2
#      INV                         : 42
#      LUT1                        : 123
#      LUT2                        : 111
#      LUT3                        : 138
#      LUT4                        : 181
#      LUT5                        : 108
#      LUT6                        : 473
#      MUXCY                       : 270
#      MUXF7                       : 66
#      VCC                         : 2
#      XORCY                       : 256
# FlipFlops/Latches                : 842
#      FDC                         : 225
#      FDCE                        : 576
#      FDE                         : 32
#      FDP                         : 7
#      FDPE                        : 2
# IO Buffers                       : 6
#      IBUF                        : 3
#      IBUFDS                      : 1
#      OBUF                        : 2
# DSPs                             : 1
#      DSP48E                      : 1
# Others                           : 1
#      endpoint_blk_plus_v1_5      : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 5vlx50tff1136-1 


Slice Logic Utilization: 
 Number of Slice Registers:            842  out of  28800     2%  
 Number of Slice LUTs:                1176  out of  28800     4%  
    Number used as Logic:             1176  out of  28800     4%  

Slice Logic Distribution: 
 Number of Bit Slices used:           1528
   Number with an unused Flip Flop     686  out of   1528    44%  
   Number with an unused LUT:          352  out of   1528    23%  
   Number of fully used Bit Slices:    490  out of   1528    32%  
   Number of unique control sets:       24

IO Utilization: 
 Number of IOs:                          7
 Number of bonded IOBs:                  7  out of    480     1%  

Specific Feature Utilization:
 Number of DSP48Es:                      1  out of     48     2%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                  | Load  |
-----------------------------------+----------------------------------------+-------+
trn_clk_c                          | NONE(app/BMD/BMD_EP/EP_RX/req_rid_o_15)| 842   |
-----------------------------------+----------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------------------------------+----------------------------------------+-------+
Control Signal                                                                         | Buffer(FF name)                        | Load  |
---------------------------------------------------------------------------------------+----------------------------------------+-------+
app/BMD/BMD_EP/EP_MEM/EP_MEM/rst_n_inv(app/BMD/BMD_EP/EP_TX/bmd_64_tx_state_Rst_inv1:O)| NONE(app/BMD/BMD_EP/EP_RX/req_rid_o_15)| 810   |
---------------------------------------------------------------------------------------+----------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 5.043ns (Maximum Frequency: 198.295MHz)
   Minimum input arrival time before clock: 4.682ns
   Maximum output required time after clock: 1.370ns
   Maximum combinational path delay: 2.788ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'trn_clk_c'
  Clock period: 5.043ns (frequency: 198.295MHz)
  Total number of paths / destination ports: 24281 / 1348
-------------------------------------------------------------------------
Delay:               5.043ns (Levels of Logic = 2)
  Source:            app/BMD/BMD_EP/EP_MEM/EP_MEM/mrd_len_o_9 (FF)
  Destination:       app/BMD/BMD_EP/EP_MEM/EP_MEM/expect_cpld_data_size_20 (FF)
  Source Clock:      trn_clk_c rising
  Destination Clock: trn_clk_c rising

  Data Path: app/BMD/BMD_EP/EP_MEM/EP_MEM/mrd_len_o_9 to app/BMD/BMD_EP/EP_MEM/EP_MEM/expect_cpld_data_size_20
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   0.471   0.352  BMD_EP/EP_MEM/EP_MEM/mrd_len_o_9 (BMD_EP/EP_MEM/EP_MEM/mrd_len_o_9)
     DSP48E:A9->P20        1   3.646   0.480  BMD_EP/EP_MEM/EP_MEM/Mmult_expect_cpld_data_size_mult0001 (BMD_EP/EP_MEM/EP_MEM/expect_cpld_data_size_mult0001<20>)
     LUT2:I1->O            1   0.094   0.000  BMD_EP/EP_MEM/EP_MEM/expect_cpld_data_size_mux0000<0>1 (BMD_EP/EP_MEM/EP_MEM/expect_cpld_data_size_mux0000<0>)
     FDC:D                    -0.018          BMD_EP/EP_MEM/EP_MEM/expect_cpld_data_size_20
    ----------------------------------------
    Total                      5.043ns (4.211ns logic, 0.832ns route)
                                       (83.5% logic, 16.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'trn_clk_c'
  Total number of paths / destination ports: 4516 / 670
-------------------------------------------------------------------------
Offset:              4.682ns (Levels of Logic = 5)
  Source:            ep:trn_rd<40> (PAD)
  Destination:       app/BMD/BMD_EP/EP_RX/req_tc_o_0 (FF)
  Destination Clock: trn_clk_c rising

  Data Path: ep:trn_rd<40> to app/BMD/BMD_EP/EP_RX/req_tc_o_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    endpoint_blk_plus_v1_5:trn_rd<40>    5   0.000   0.000  ep (trn_rd_c<40>)
     begin scope: 'app/BMD'
     LUT6:I0->O            1   0.094   0.480  BMD_EP/EP_RX/req_tc_o_not0001144 (BMD_EP/EP_RX/req_tc_o_not00011_map19)
     LUT6:I5->O            1   0.094   0.973  BMD_EP/EP_RX/req_tc_o_not00011114 (BMD_EP/EP_RX/req_tc_o_not00011_map24)
     LUT6:I1->O            4   0.094   1.085  BMD_EP/EP_RX/req_tc_o_not00011219 (N162)
     LUT6:I0->O           36   0.094   0.464  BMD_EP/EP_RX/req_tc_o_not00011 (BMD_EP/EP_RX/req_tc_o_not0001)
     FDCE:CE                   0.213          BMD_EP/EP_RX/req_tc_o_0
    ----------------------------------------
    Total                      4.682ns (1.680ns logic, 3.002ns route)
                                       (35.9% logic, 64.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'trn_clk_c'
  Total number of paths / destination ports: 83 / 79
-------------------------------------------------------------------------
Offset:              1.370ns (Levels of Logic = 2)
  Source:            app/BMD/BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1 (FF)
  Destination:       ep:cfg_interrupt_n (PAD)
  Source Clock:      trn_clk_c rising

  Data Path: app/BMD/BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1 to ep:cfg_interrupt_n
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.471   0.805  BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1 (BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1)
     LUT4:I0->O            0   0.094   0.000  BMD_EP/EP_TX/BMD_INTR_CTRL/cfg_interrupt_n_o1 (cfg_interrupt_n)
     end scope: 'app/BMD'
    endpoint_blk_plus_v1_5:cfg_interrupt_n        0.000          ep
    ----------------------------------------
    Total                      1.370ns (0.565ns logic, 0.805ns route)
                                       (41.2% logic, 58.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 23 / 14
-------------------------------------------------------------------------
Delay:               2.788ns (Levels of Logic = 1)
  Source:            ep:pci_exp_txn<0> (PAD)
  Destination:       pci_exp_txn<0> (PAD)

  Data Path: ep:pci_exp_txn<0> to pci_exp_txn<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    endpoint_blk_plus_v1_5:pci_exp_txn<0>    1   0.000   0.336  ep (pci_exp_txn)
     OBUF:I->O                 2.452          pci_exp_txn_0_OBUF (pci_exp_txn<0>)
    ----------------------------------------
    Total                      2.788ns (2.452ns logic, 0.336ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX 1": Did not attach to ep.
CPU : 174.63 / 174.69 s | Elapsed : 177.00 / 177.00 s
 
--> 


Total memory usage is 294868 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   80 (   0 filtered)
Number of infos    :    2 (   0 filtered)