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Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Requirement: 4.000ns Data Path Delay: 3.766ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------------- ------------------- RAMB36_X1Y9.DOBDOL10 Trcko_DO 0.922 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst PCIE_X0Y0.MIMDLLBRDATA52 net (fanout=1) 2.886 ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_brdata<52> PCIE_X0Y0.CRMCORECLK Tpcidck_DLRETRY -0.042 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ----------------------------------------------------- --------------------------- Total 3.766ns (0.880ns logic, 2.886ns route) (23.4% logic, 76.6% route)--------------------------------------------------------------------------------Slack: 0.219ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Requirement: 4.000ns Data Path Delay: 3.746ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------------- ------------------- RAMB36_X1Y9.DOADOL15 Trcko_DO 0.922 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst PCIE_X0Y0.MIMDLLBRDATA30 net (fanout=1) 2.869 ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_brdata<30> PCIE_X0Y0.CRMCORECLK Tpcidck_DLRETRY -0.045 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ----------------------------------------------------- --------------------------- Total 3.746ns (0.877ns logic, 2.869ns route) (23.4% logic, 76.6% route)--------------------------------------------------------------------------------Slack: 0.229ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.736ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAU3 net (fanout=20) 2.483 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKU Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.736ns (1.253ns logic, 2.483ns route) (33.5% logic, 66.5% route)--------------------------------------------------------------------------------Slack: 0.229ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.736ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAU2 net (fanout=20) 2.483 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKU Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.736ns (1.253ns logic, 2.483ns route) (33.5% logic, 66.5% route)--------------------------------------------------------------------------------Slack: 0.229ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.736ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAL2 net (fanout=20) 2.483 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKL Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.736ns (1.253ns logic, 2.483ns route) (33.5% logic, 66.5% route)--------------------------------------------------------------------------------Slack: 0.229ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.736ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAL3 net (fanout=20) 2.483 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKL Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.736ns (1.253ns logic, 2.483ns route) (33.5% logic, 66.5% route)--------------------------------------------------------------------------------Slack: 0.230ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/prod_fixes_I/upcfgcap_cycle (FF) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Requirement: 4.000ns Data Path Delay: 3.735ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: ⌨️ 快捷键说明
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