routed.twr

基于xilinx vierex5得pci express dma设计实现。

                                                           ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg_10
    GTP_DUAL_X0Y1.TXDATA12   net (fanout=1)        2.213   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg<10>
    GTP_DUAL_X0Y1.TXUSRCLK21 Tgtpcck_TXDATA       -0.827   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
    -----------------------------------------------------  ---------------------------
    Total                                          1.836ns (-0.377ns logic, 2.213ns route)
                                                           (-20.5% logic, 120.5% route)

--------------------------------------------------------------------------------
Slack:                  0.135ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_chanisaligned_reg_0 (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.830ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_chanisaligned_reg_0 to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                        Delay type         Delay(ns)  Physical Resource
                                                                  Logical Resource(s)
    ------------------------------------------------------------  -------------------
    SLICE_X59Y37.AQ                 Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_valid_reg<1>
                                                                  ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_chanisaligned_reg_0
    PCIE_X0Y0.PIPERXCHANISALIGNEDL0 net (fanout=1)        2.876   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_chanisaligned_reg<0>
    PCIE_X0Y0.CRMCORECLK            Tpcicck_MGT           0.504   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                                  ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    ------------------------------------------------------------  ---------------------------
    Total                                                 3.830ns (0.954ns logic, 2.876ns route)
                                                                  (24.9% logic, 75.1% route)

--------------------------------------------------------------------------------
Slack:                  0.139ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_data_k_reg_0 (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.826ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_data_k_reg_0 to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                Delay type         Delay(ns)  Physical Resource
                                                          Logical Resource(s)
    ----------------------------------------------------  -------------------
    SLICE_X58Y36.AQ         Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_phy_status_reg<1>
                                                          ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_data_k_reg_0
    PCIE_X0Y0.PIPERXDATAKL0 net (fanout=1)        2.967   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_data_k_reg<0>
    PCIE_X0Y0.CRMCORECLK    Tpcicck_MGT           0.409   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    ----------------------------------------------------  ---------------------------
    Total                                         3.826ns (0.859ns logic, 2.967ns route)
                                                          (22.5% logic, 77.5% route)

--------------------------------------------------------------------------------
Slack:                  0.180ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.785ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    RAMB36_X1Y9.DOBDOL1      Trcko_DO              0.922   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
    PCIE_X0Y0.MIMDLLBRDATA34 net (fanout=1)        2.846   ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_brdata<34>
    PCIE_X0Y0.CRMCORECLK     Tpcidck_DLRETRY       0.017   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    -----------------------------------------------------  ---------------------------
    Total                                          3.785ns (0.939ns logic, 2.846ns route)
                                                           (24.8% logic, 75.2% route)

--------------------------------------------------------------------------------
Slack:                  0.181ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst (RAM)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.784ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location               Delay type         Delay(ns)  Physical Resource
                                                         Logical Resource(s)
    ---------------------------------------------------  -------------------
    RAMB36_X1Y6.DOBDOL2    Trcko_DOB             0.818   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
                                                         ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
    PCIE_X0Y0.MIMTXBRDATA4 net (fanout=1)        2.853   ep/BU2/U0/pcie_ep0/pcie_blk/mim_tx_brdata<4>
    PCIE_X0Y0.CRMCORECLK   Tpcidck_TXRAM         0.113   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                         ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    ---------------------------------------------------  ---------------------------
    Total                                        3.784ns (0.931ns logic, 2.853ns route)
                                                         (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------
Slack:                  0.182ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.783ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    RAMB36_X1Y9.DOADOL12     Trcko_DO              0.922   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
    PCIE_X0Y0.MIMDLLBRDATA24 net (fanout=1)        2.894   ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_brdata<24>
    PCIE_X0Y0.CRMCORECLK     Tpcidck_DLRETRY      -0.033   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    -----------------------------------------------------  ---------------------------
    Total                                          3.783ns (0.889ns logic, 2.894ns route)
                                                           (23.5% logic, 76.5% route)

--------------------------------------------------------------------------------
Slack:                  0.198ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.767ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    RAMB36_X1Y9.DOBDOL6      Trcko_DO              0.922   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
    PCIE_X0Y0.MIMDLLBRDATA44 net (fanout=1)        2.776   ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_brdata<44>
    PCIE_X0Y0.CRMCORECLK     Tpcidck_DLRETRY       0.069   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    -----------------------------------------------------  ---------------------------
    Total                                          3.767ns (0.991ns logic, 2.776ns route)
                                                           (26.3% logic, 73.7% route)

--------------------------------------------------------------------------------
Slack:                  0.199ns (requirement - (data path - clock path skew + uncertainty))