📄 routed.twr
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Data Path Delay: 3.941ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMTXBREN Tpcicko_TXRAM 0.743 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y6.ENBWRENL net (fanout=4) 2.784 ep/BU2/U0/pcie_ep0/pcie_blk/mim_tx_bren RAMB36_X1Y6.CLKBWRCLKL Trcck_ENB 0.414 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.941ns (1.157ns logic, 2.784ns route) (29.4% logic, 70.6% route)--------------------------------------------------------------------------------Slack: 0.026ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.939ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAL0 net (fanout=20) 2.686 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKL Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.939ns (1.253ns logic, 2.686ns route) (31.8% logic, 68.2% route)--------------------------------------------------------------------------------Slack: 0.026ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.939ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAU0 net (fanout=20) 2.686 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKU Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.939ns (1.253ns logic, 2.686ns route) (31.8% logic, 68.2% route)--------------------------------------------------------------------------------Slack: 0.026ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.939ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAU1 net (fanout=20) 2.686 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKU Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.939ns (1.253ns logic, 2.686ns route) (31.8% logic, 68.2% route)--------------------------------------------------------------------------------Slack: 0.026ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.939ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- PCIE_X0Y0.MIMRXBWEN Tpcicko_RXRAM 0.629 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.WEAL1 net (fanout=20) 2.686 ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_bwen RAMB36_X1Y5.CLKARDCLKL Trcck_WEA 0.624 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst --------------------------------------------------- --------------------------- Total 3.939ns (1.253ns logic, 2.686ns route) (31.8% logic, 68.2% route)--------------------------------------------------------------------------------Slack: 0.047ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/extend_clk/l0_dll_error_vector_d_1 (FF) Requirement: 4.000ns Data Path Delay: 3.918ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/extend_clk/l0_dll_error_vector_d_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------------- ------------------- PCIE_X0Y0.L0DLLERRORVECTOR1 Tpcicko_CFG 1.436 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep SLICE_X51Y63.BX net (fanout=2) 2.493 ep/BU2/U0/pcie_ep0/fe_l0_dll_error_vector<1> SLICE_X51Y63.CLK Tdick -0.011 ep/BU2/U0/pcie_ep0/extend_clk/l0_dll_error_vector_ddd<2> ep/BU2/U0/pcie_ep0/extend_clk/l0_dll_error_vector_d_1 -------------------------------------------------------- --------------------------- Total 3.918ns (1.425ns logic, 2.493ns route) (36.4% logic, 63.6% route)--------------------------------------------------------------------------------Slack: 0.066ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst (RAM) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Requirement: 4.000ns Data Path Delay: 3.899ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns Destination Clock: ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns⌨️ 快捷键说明
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