routed.twr

基于xilinx vierex5得pci express dma设计实现。

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Release 9.2.03i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

trce -u -v 100 routed.ncd mapped.pcf

Design file:              routed.ncd
Physical constraint file: mapped.pcf
Device,package,speed:     xc5vlx50t,ff1136,-1 (PRODUCTION 1.57 2007-08-28, STEPPING level ES)
Report level:             verbose report, limited to 100 items per constraint
                          unconstrained path report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: NET "sys_clk_c" PERIOD = 10 ns HIGH 50%;

 0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: PERIOD analysis for net 
"ep/BU2/U0/pcie_ep0/pcie_blk/clocking_i/clkout0" derived from  NET "sys_clk_c" 
PERIOD = 10 ns HIGH 50%;  divided by 2.50  to 4 nS   

 610 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   3.993ns.
--------------------------------------------------------------------------------
Slack:                  0.006ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg_14 (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i (HSIO)
  Requirement:          2.000ns
  Data Path Delay:      1.959ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk falling at 2.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg_14 to ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    SLICE_X59Y49.BQ          Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg<11>
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg_14
    GTP_DUAL_X0Y1.TXDATA16   net (fanout=1)        2.336   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg<14>
    GTP_DUAL_X0Y1.TXUSRCLK21 Tgtpcck_TXDATA       -0.827   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
    -----------------------------------------------------  ---------------------------
    Total                                          1.959ns (-0.377ns logic, 2.336ns route)
                                                           (-19.2% logic, 119.2% route)

--------------------------------------------------------------------------------
Slack:                  0.007ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst (RAM)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.958ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                Delay type         Delay(ns)  Physical Resource
                                                          Logical Resource(s)
    ----------------------------------------------------  -------------------
    RAMB36_X1Y6.DOBDOL9     Trcko_DOB             0.818   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
                                                          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
    PCIE_X0Y0.MIMTXBRDATA18 net (fanout=1)        3.034   ep/BU2/U0/pcie_ep0/pcie_blk/mim_tx_brdata<18>
    PCIE_X0Y0.CRMCORECLK    Tpcidck_TXRAM         0.106   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    ----------------------------------------------------  ---------------------------
    Total                                         3.958ns (0.924ns logic, 3.034ns route)
                                                          (23.3% logic, 76.7% route)

--------------------------------------------------------------------------------
Slack:                  0.011ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg_9 (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i (HSIO)
  Requirement:          2.000ns
  Data Path Delay:      1.954ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk falling at 2.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg_9 to ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    SLICE_X58Y50.DQ          Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg<9>
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg_9
    GTP_DUAL_X0Y1.TXDATA11   net (fanout=1)        2.331   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_tx_data_reg<9>
    GTP_DUAL_X0Y1.TXUSRCLK21 Tgtpcck_TXDATA       -0.827   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i
    -----------------------------------------------------  ---------------------------
    Total                                          1.954ns (-0.377ns logic, 2.331ns route)
                                                           (-19.3% logic, 119.3% route)

--------------------------------------------------------------------------------
Slack:                  0.012ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.953ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    RAMB36_X1Y9.DOBDOU11     Trcko_DO              0.818   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
    PCIE_X0Y0.MIMDLLBRDATA55 net (fanout=1)        3.228   ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_brdata<55>
    PCIE_X0Y0.CRMCORECLK     Tpcidck_DLRETRY      -0.093   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                           ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    -----------------------------------------------------  ---------------------------
    Total                                          3.953ns (0.725ns logic, 3.228ns route)
                                                           (18.3% logic, 81.7% route)

--------------------------------------------------------------------------------
Slack:                  0.024ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst (RAM)
  Requirement:          4.000ns
  Data Path Delay:      3.941ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         ep/BU2/U0/pcie_ep0/core_clk rising at 0.000ns
  Destination Clock:    ep/BU2/U0/pcie_ep0/core_clk rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
    Location               Delay type         Delay(ns)  Physical Resource
                                                         Logical Resource(s)
    ---------------------------------------------------  -------------------
    PCIE_X0Y0.MIMTXBREN    Tpcicko_TXRAM         0.743   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                         ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    RAMB36_X1Y6.ENBU       net (fanout=4)        2.784   ep/BU2/U0/pcie_ep0/pcie_blk/mim_tx_bren
    RAMB36_X1Y6.CLKBWRCLKU Trcck_ENB             0.414   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
                                                         ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
    ---------------------------------------------------  ---------------------------
    Total                                        3.941ns (1.157ns logic, 2.784ns route)
                                                         (29.4% logic, 70.6% route)

--------------------------------------------------------------------------------
Slack:                  0.024ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst (RAM)
  Requirement:          4.000ns