mapped.map

基于xilinx vierex5得pci express dma设计实现。

Release 9.2.03i Map J.39
Xilinx Map Application Log File for Design 'xilinx_pci_exp_1_lane_ep'

Design Information
------------------
Command Line   : map -timing -ol high -xe c -pr b -o mapped.ncd
endpoint_blk_plus_v1_5_top.ngd mapped.pcf 
Target Device  : xc5vlx50t
Target Package : ff1136
Target Speed   : -1
Stepping Level : ES (Set by "XIL_MAP_SETSTEPPING" env)
Mapper Version : virtex5 -- $Revision: 1.36 $
Mapped Date    : Sun Nov 18 08:07:06 2007

Mapping design into LUTs...
Writing file mapped.ngm...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:9b01e1) REAL time: 1 mins 58 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 1 mins 58 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 1 mins 58 secs 

Phase 4.33
Phase 4.33 (Checksum:26259fc) REAL time: 4 mins 23 secs 

Phase 5.32
Phase 5.32 (Checksum:2faf07b) REAL time: 4 mins 25 secs 

Phase 6.2
.
Phase 6.2 (Checksum:39386fa) REAL time: 4 mins 42 secs 

Phase 7.30
Phase 7.30 (Checksum:42c1d79) REAL time: 4 mins 42 secs 

Phase 8.3
Phase 8.3 (Checksum:4c4b3f8) REAL time: 4 mins 45 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 4 mins 46 secs 

Phase 10.8
.....................................
.......
..................................
...............
...............
...............
Phase 10.8 (Checksum:1cdacde) REAL time: 6 mins 38 secs 

Phase 11.29
Phase 11.29 (Checksum:68e7775) REAL time: 6 mins 38 secs 

Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 6 mins 38 secs 

Phase 13.18
Phase 13.18 (Checksum:7bfa473) REAL time: 12 mins 24 secs 

Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 12 mins 24 secs 

Phase 16.34
Phase 16.34 (Checksum:98967f0) REAL time: 12 mins 24 secs 

REAL time consumed by placer: 12 mins 25 secs 
CPU  time consumed by placer: 12 mins 25 secs 
Inspecting route info ...
Route info done.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    4
Slice Logic Utilization:
  Number of Slice Registers:                 2,857 out of  28,800    9%
    Number used as Flip Flops:               2,856
    Number used as Latches:                      1
  Number of Slice LUTs:                      2,794 out of  28,800    9%
    Number used as logic:                    2,574 out of  28,800    8%
      Number using O6 output only:           2,318
      Number using O5 output only:             137
      Number using O5 and O6:                  119
    Number used as Memory:                     204 out of   7,680    2%
      Number used as Dual Port RAM:            136
        Number using O6 output only:             8
        Number using O5 output only:            64
        Number using O5 and O6:                 64
      Number used as Shift Register:            68
        Number using O6 output only:            68
    Number used as exclusive route-thru:        16
  Number of route-thrus:                       167 out of  57,600    1%
    Number using O6 output only:               152
    Number using O5 output only:                14
    Number using O5 and O6:                      1

Slice Logic Distribution:
  Number of occupied Slices:                 1,537 out of   7,200   21%
  Number of LUT Flip Flop pairs used:        3,873
    Number with an unused Flip Flop:         1,016 out of   3,873   26%
    Number with an unused LUT:               1,079 out of   3,873   27%
    Number of fully used LUT-FF pairs:       1,778 out of   3,873   45%
    Number of unique control sets:             208

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         1 out of     480    1%

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                       6 out of      60   10%
    Number using BlockRAM only:                  6
    Total primitives used:
      Number of 36k BlockRAM used:               6
    Total Memory used (KB):                    216 out of   2,160   10%
  Number of BUFG/BUFGCTRLs:                      4 out of      32   12%
    Number used as BUFGs:                        4
  Number of BUFDSs:                              1 out of       6   16%
  Number of DSP48Es:                             1 out of      48    2%
  Number of GTP_DUALs:                           1 out of       6   16%
  Number of PCIEs:                               1 out of       1  100%
  Number of PLL_ADVs:                            1 out of       6   16%

Total equivalent gate count for design:  862,904
Additional JTAG gate count for IOBs:  336
Peak Memory Usage:  434 MB
Total REAL time to MAP completion:  16 mins 12 secs 
Total CPU time to MAP completion:   16 mins 11 secs 

Mapping completed.
See MAP report file "mapped.mrp" for details.