timing.twr

基于xilinx vierex5得pci express dma设计实现。

Number of Timing Constraints that were not applied: 5

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

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  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
* PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.109ns|    15.564ns|       0|           0
  p0/pcie_blk/clocking_i/clkout1" derived f | HOLD    |    -0.534ns|            |      66|       12515
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
* PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.109ns|    15.564ns|       0|           0
  p0/pcie_blk/clocking_i/clkout1" derived f | HOLD    |    -0.534ns|            |      66|       12515
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.006ns|     3.988ns|       0|           0
  p0/pcie_blk/clocking_i/clkout0" derived f | HOLD    |     0.002ns|            |       0|           0
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  NET "sys_clk_c" PERIOD = 10 ns HIGH 50%   | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ep/BU2/U0/pcie_e | N/A     |         N/A|         N/A|     N/A|         N/A
  p0/pcie_blk/clocking_i/clkout0" derived f |         |            |            |        |            
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_MGTCLK = PERIOD TIMEGRP "MGTCLK" 100 M | N/A     |         N/A|         N/A|     N/A|         N/A
  Hz HIGH 50%                               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_ep_BU2_U0_pcie_ep0_pcie_blk_clocking_i | N/A     |         N/A|         N/A|     N/A|         N/A
  _clkout0 = PERIOD TIMEGRP         "ep_BU2 |         |            |            |        |            
  _U0_pcie_ep0_pcie_blk_clocking_i_clkout0" |         |            |            |        |            
   TS_MGTCLK * 2.5 HIGH         50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_ep_BU2_U0_pcie_ep0_pcie_blk_clocking_i | N/A     |         N/A|         N/A|     N/A|         N/A
  _clkout1 = PERIOD TIMEGRP         "ep_BU2 |         |            |            |        |            
  _U0_pcie_ep0_pcie_blk_clocking_i_clkout1" |         |            |            |        |            
   TS_MGTCLK * 0.625         HIGH 50%       |         |            |            |        |            
------------------------------------------------------------------------------------------------------


2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.