routed.par

基于xilinx vierex5得pci express dma设计实现。

Release 9.2.03i par J.39
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

forever-s1::  Sun Nov 18 08:23:19 2007

par -ol high -xe c -w mapped.ncd routed.ncd mapped.pcf 

INFO:Par:338 - 
   Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is
   intended to be used for designs that are not meeting timing but where the
   designer wants the tools to continue iterating on the design until no further
   design speed improvements are possible.  This can result in very long
   runtimes since the tools will continue improving the design even if the time
   specs can not be met. If you are looking for the best possible design speed
   available from a long but reasonable runtime use Extra Effort Level "n"ormal.
    It will stop iterating on the design when the design speed improvements have
   shrunk to the point that the time specs are not expected to be met.

Constraints file: mapped.pcf.
Loading device for application Rf_Device from file '5vlx50t.nph' in environment /program/ise92.
   "xilinx_pci_exp_1_lane_ep" is an NCD, version 3.1, device xc5vlx50t, package ff1136, speed -1
The STEPPING level for this design is ES.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)


Device speed data version:  "PRODUCTION 1.57 2007-08-28".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.

Device Utilization Summary:

   Number of BUFDSs                          1 out of 6      16%
   Number of BUFGs                           4 out of 32     12%
   Number of DSP48Es                         1 out of 48      2%
   Number of GTP_DUALs                       1 out of 6      16%
      Number of LOCed GTP_DUALs              1 out of 1     100%

   Number of External IOBs                   1 out of 480     1%
      Number of LOCed IOBs                   1 out of 1     100%

   Number of External IPADs                  4 out of 518     1%
      Number of LOCed IPADs                  2 out of 4      50%

   Number of External OPADs                  2 out of 24      8%
      Number of LOCed OPADs                  0 out of 2       0%

   Number of PCIEs                           1 out of 1     100%
   Number of PLL_ADVs                        1 out of 6      16%
   Number of RAMB36SDP_EXPs                  2 out of 60      3%
      Number of LOCed RAMB36SDP_EXPs         1 out of 2      50%

   Number of RAMB36_EXPs                     4 out of 60      6%
      Number of LOCed RAMB36_EXPs            4 out of 4     100%

   Number of Slice Registers              2858 out of 28800   9%
      Number used as Flip Flops           2857
      Number used as Latches                 1
      Number used as LatchThrus              0

   Number of Slice LUTS                   2794 out of 28800   9%
   Number of Slice LUT-Flip Flop pairs    3873 out of 28800  13%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 43 secs 
Finished initial Timing Analysis.  REAL time: 43 secs 

Starting Router

Phase 1: 20173 unrouted;       REAL time: 45 secs 

Phase 2: 17068 unrouted;       REAL time: 49 secs 

Phase 3: 6217 unrouted;       REAL time: 1 mins 5 secs 

Phase 4: 6217 unrouted; (23399)      REAL time: 1 mins 6 secs 

Phase 5: 6220 unrouted; (22348)      REAL time: 1 mins 8 secs 

Phase 6: 6220 unrouted; (22348)      REAL time: 1 mins 9 secs 

Phase 7: 0 unrouted; (25030)      REAL time: 2 mins 16 secs 

Updating file: routed.ncd with current fully routed design.

Phase 8: 0 unrouted; (25030)      REAL time: 2 mins 33 secs 

Phase 9: 0 unrouted; (25030)      REAL time: 2 mins 36 secs 

Phase 10: 0 unrouted; (25030)      REAL time: 3 mins 35 secs 

Phase 11: 0 unrouted; (0)      REAL time: 3 mins 40 secs 

Total REAL time to Router completion: 3 mins 40 secs 
Total CPU time to Router completion: 3 mins 40 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|ep/BU2/U0/pcie_ep0/c |              |      |      |            |             |
|             ore_clk | BUFGCTRL_X0Y9| No   |   73 |  0.227     |  1.808      |
+---------------------+--------------+------+------+------------+-------------+
|           trn_clk_c | BUFGCTRL_X0Y4| No   | 1324 |  0.335     |  1.843      |
+---------------------+--------------+------+------+------------+-------------+
|ep/BU2/U0/pcie_ep0/p |              |      |      |            |             |
|cie_blk/SIO/.pcie_gt |              |      |      |            |             |
|_wrapper_i/icdrreset |              |      |      |            |             |
|                 <0> |         Local|      |    1 |  0.000     |  0.480      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.351
   The MAXIMUM PIN DELAY IS:                               5.851
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   4.735

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
        7447        6469        2453         605         225           0

Timing Score: 0

Number of Timing Constraints that were not applied: 5

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.006ns|     3.993ns|       0|           0
  p0/pcie_blk/clocking_i/clkout0" derived f | HOLD    |     0.393ns|            |       0|           0
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.109ns|    15.564ns|       0|           0
  p0/pcie_blk/clocking_i/clkout1" derived f | HOLD    |     0.303ns|            |       0|           0
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.109ns|    15.564ns|       0|           0
  p0/pcie_blk/clocking_i/clkout1" derived f | HOLD    |     0.303ns|            |       0|           0
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  NET "sys_clk_c" PERIOD = 10 ns HIGH 50%   | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "ep/BU2/U0/pcie_e | N/A     |         N/A|         N/A|     N/A|         N/A
  p0/pcie_blk/clocking_i/clkout0" derived f |         |            |            |        |            
  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |            
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_MGTCLK = PERIOD TIMEGRP "MGTCLK" 100 M | N/A     |         N/A|         N/A|     N/A|         N/A
  Hz HIGH 50%                               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_ep_BU2_U0_pcie_ep0_pcie_blk_clocking_i | N/A     |         N/A|         N/A|     N/A|         N/A
  _clkout0 = PERIOD TIMEGRP         "ep_BU2 |         |            |            |        |            
  _U0_pcie_ep0_pcie_blk_clocking_i_clkout0" |         |            |            |        |            
   TS_MGTCLK * 2.5 HIGH         50%         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_ep_BU2_U0_pcie_ep0_pcie_blk_clocking_i | N/A     |         N/A|         N/A|     N/A|         N/A
  _clkout1 = PERIOD TIMEGRP         "ep_BU2 |         |            |            |        |            
  _U0_pcie_ep0_pcie_blk_clocking_i_clkout1" |         |            |            |        |            
   TS_MGTCLK * 0.625         HIGH 50%       |         |            |            |        |            
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 mins 45 secs 
Total CPU time to PAR completion: 3 mins 45 secs 

Peak Memory Usage:  349 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 3

Writing design to file routed.ncd



PAR done!