modelsim.ini

基于xilinx vierex5得pci express dma设计实现。

; Copyright 2006 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;   

[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release

UNISIM = /program/simlib/ise_edk92/unisim
SIMPRIM = /program/simlib/ise_edk92/simprim
XILINXCORELIB = /program/simlib/ise_edk92/XilinxCoreLib


UNISIMS_VER = /program/simlib/ise_edk92/unisims_ver
UNI9000_VER = /program/simlib/ise_edk92/uni9000_ver
SIMPRIMS_VER = /program/simlib/ise_edk92/simprims_ver
XILINXCORELIB_VER = /program/simlib/ise_edk92/XilinxCoreLib_ver
AIM_VER = /program/simlib/ise_edk92/abel_ver/aim_ver
CPLD_VER = /program/simlib/ise_edk92/cpld_ver
AIM = /program/simlib/ise_edk92/abel/aim
PLS = /program/simlib/ise_edk92/abel/pls
CPLD = /program/simlib/ise_edk92/cpld
[vcom]
; VHDL93 variable selects language version as the default. 
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002

; Show source line containing error. Default is off.
; Show_source = 1

; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1

; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1

; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0

; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0

; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1

; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1

; Treat as errors:
;   case statement static warnings
;   warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1

; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:
;    -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Turns on lint-style checking.
; Show_Lint = 1

; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1

; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile=1;

; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1

; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1

; Run the 0in tools from within the simulator. 
; Default value set to 0. Please set it to 1 to invoke 0in.
; VcomZeroIn = 1

; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VcomZeroInOptions = ""

; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageNoSub = 0

; Automatically exclude VHDL case statement default branches. 
; Default is to not exclude.
; CoverExcludeDefault = 1

; Turn on code coverage in VHDL generate blocks. Default is off.
; CoverGenerate = 1

; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp

[vlog]

; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Turns on lint-style checking.
; Show_Lint = 1

; Show source line containing error. Default is off.
; Show_source = 1

; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1

; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
vlog95compat = 0

; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0

; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code.
; The default is 0 (i.e. no memory is automatically given sparse status)
; SparseMemThreshold = 1048576 

; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000

; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200

; Run the 0in tools from within the simulator. 
; Default value set to 0. Please set it to 1 to invoke 0in.
; VlogZeroIn = 1

; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VlogZeroInOptions = ""

; Run the 0in tools from within the simulator. 
; Default value set to 0. Please set it to 1 to invoke 0in.
; VoptZeroIn = 1

; Set the options to be passed to the 0in tools.
; Default value set to "". Please set it to appropriate options needed.
; VoptZeroInOptions = ""

; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1

; Automatically exclude Verilog case statement default branches. 
; Default is to not exclude.
; CoverExcludeDefault = 1

; Turn on code coverage in VLOG generate blocks. Default is off.
; CoverGenerate = 1

; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0

; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0

; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with 
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
;    variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr

[sccom]
; Enable use of SCV include files and library.  Default is off.
; UseScv = 1

; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g

; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++

; Enable verbose messages from sccom.  Default is off.
; SccomVerbose = 1

; sccom logfile.  Default is no logfile.
; SccomLogfile = sccom.log

; Enable use of SC_MS include files and library.  Default is off.
; UseScMs = 1

[vsim]

; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1

; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0

; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps

; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default

; Default run length
RunLength = 100

; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000

; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1 

; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
;    -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1 
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1 

; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl          Immediately reserve a VHDL license
; vlog          Immediately reserve a Verilog license
; plus          Immediately reserve a VHDL and Verilog license
; nomgc         Do not look for Mentor Graphics Licenses
; nomti         Do not look for Model Technology Licenses
; noqueue       Do not wait in the license queue when a license is not available
; viewsim       Try for viewer license but accept simulator license(s) instead
;               of queuing for viewer license (PE ONLY)
; noviewer	Disable checkout of msimviewer and vsim-viewer license 
;		features (PE ONLY)
; noslvhdl	Disable checkout of qhsimvh and vsim license features
; noslvlog	Disable checkout of qhsimvl and vsimvlog license features
; nomix		Disable checkout of msimhdlmix and hdlmix license features
; nolnl		Disable checkout of msimhdlsim and hdlsim license features
; mixedonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license 
;		features
; lnlonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
;		hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus

; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; VHDL assertion Message Format
; %S - Severity Level 
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
;      from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use AssertionFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
;   level), use AssertionFormatBreak;
; - otherwise, use AssertionFormat.
; AssertionFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
; AssertionFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; AssertionFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; AssertionFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; AssertionFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; AssertionFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; AssertionFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; AssertionFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log


; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name:  # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1


; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic