pio_tests.v

基于xilinx vierex5得pci express dma设计实现。

       				
		     end
		2'b11 : // MEM 64 SPACE 			
		     begin

		       $display("[%t] : Transmitting TLPs to Memory 64 Space BAR %x", $realtime, ii);



		       //--------------------------------------------------------------------------
		       // Event : Memory Write 64 bit TLPs
		       //--------------------------------------------------------------------------

		       TSK_TX_MEMORY_WRITE_64(DEFAULT_TAG, DEFAULT_TC, 10'd1, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'h0, 4'hF, 1'b0);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_WRITE_64(DEFAULT_TAG, DEFAULT_TC, 10'd16, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF, 1'b0);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_WRITE_64(DEFAULT_TAG, DEFAULT_TC, 10'd32, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF, 1'b0);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_WRITE_64(DEFAULT_TAG, DEFAULT_TC, 10'd64, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF, 1'b0);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_WRITE_64(DEFAULT_TAG, DEFAULT_TC, 10'd128, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF, 1'b0);
		       TSK_TX_CLK_EAT(1000);
		       DEFAULT_TAG = DEFAULT_TAG + 1;


		       //--------------------------------------------------------------------------
		       // Event : Memory Read 64 bit TLPs
		       //--------------------------------------------------------------------------

         	       TSK_TX_MEMORY_READ_64(DEFAULT_TAG, DEFAULT_TC, 10'd1, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'h0, 4'hF);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_READ_64(DEFAULT_TAG, DEFAULT_TC, 10'd16, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_READ_64(DEFAULT_TAG, DEFAULT_TC, 10'd32, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_READ_64(DEFAULT_TAG, DEFAULT_TC, 10'd64, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF);
		       TSK_TX_CLK_EAT(10);
		       DEFAULT_TAG = DEFAULT_TAG + 1;

		       TSK_TX_MEMORY_READ_64(DEFAULT_TAG, DEFAULT_TC, 10'd128, {BAR_INIT_P_BAR[ii+1][31:0], BAR_INIT_P_BAR[ii][31:0]}, 4'hF, 4'hF);
		       TSK_TX_CLK_EAT(1000);
		       DEFAULT_TAG = DEFAULT_TAG + 1;


			   
        	     end
		default : $display("Error case in usrapp_tx\n");
	    endcase
	          
	 end


	$display("[%t] : Transmitting Completion TLPs", $realtime);


    //--------------------------------------------------------------------------
    // Event # 13: Completion TLP
    //--------------------------------------------------------------------------

    $display("[%t] : Sending PCI-Express COMPLETION TLPs", $realtime);

    TSK_TX_COMPLETION(DEFAULT_TAG, DEFAULT_TC, 10'd6, 3'h0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(10);

    //--------------------------------------------------------------------------
    // Event # 14: Completion with Data TLPs
    //--------------------------------------------------------------------------

    TSK_TX_COMPLETION_DATA(DEFAULT_TAG, DEFAULT_TC, 2, 12'hF, 7'b011_0101, 3'h0, 1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(10);

    TSK_TX_COMPLETION_DATA(DEFAULT_TAG, DEFAULT_TC, 16, 12'hF, 7'b011_0101, 3'h0, 1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(10);

    TSK_TX_COMPLETION_DATA(DEFAULT_TAG, DEFAULT_TC, 32, 12'hF, 7'b011_0101, 3'h0, 1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(10);

    TSK_TX_COMPLETION_DATA(DEFAULT_TAG, DEFAULT_TC, 5, 12'hF, 7'b011_0101, 3'h0, 1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(10);

    $display("[%t] : Finished transmission of PCI-Express TLPs", $realtime);
    $finish;
end

else if(testname == "pio_timeoutFailureExpected")
begin

    // This test performs a 32 bit write to an illegal 32 bit Memory space address and performs a read back
    // The task TSK_WAIT_FOR_READ_DATA should time out.

    TSK_SIMULATION_TIMEOUT(10050);

    TSK_SYSTEM_INITIALIZATION;

    TSK_BAR_INIT;

//--------------------------------------------------------------------------
// Event : Testing Mem32 BARs
//--------------------------------------------------------------------------


	for (ii = 0; ii <= 6; ii = ii + 1) begin 
	    if (BAR_INIT_P_BAR_ENABLED[ii] > 2'b00) // bar is enabled
               case(BAR_INIT_P_BAR_ENABLED[ii])
		   2'b01 : // IO SPACE
			begin

			  $display("[%t] : NOTHING: to IO 32 Space BAR %x", $realtime, ii);
			
		        end
			   
		   2'b10 : // MEM 32 SPACE
			begin

			  cpld_to_finish = 0; // Turn off TSK_WAIT_FOR_READ_DATA's finish on timeout default mechanism
			  

		          $display("[%t] : Transmitting TLPs to Memory 32 Space BAR %x", $realtime, ii);

			  //--------------------------------------------------------------------------
			  // Event : Memory Write 32 bit TLP
			  //--------------------------------------------------------------------------

                          DATA_STORE[0] = 8'h04;
                          DATA_STORE[1] = 8'h03;
                          DATA_STORE[2] = 8'h02;
                          DATA_STORE[3] = 8'h01;
                          P_READ_DATA = 32'hffff_ffff; // make sure P_READ_DATA has known initial value
			  // Note that 32'h8000_0000 will most likely be unused memory space
			  TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC, 10'd1, 32'h8000_0000, 4'h0, 4'hF, 1'b0);
			  TSK_TX_CLK_EAT(10);
			  DEFAULT_TAG = DEFAULT_TAG + 1;			   

			  //--------------------------------------------------------------------------
			  // Event : Memory Read 32 bit TLP
			  //--------------------------------------------------------------------------


			  TSK_TX_MEMORY_READ_32(DEFAULT_TAG, DEFAULT_TC, 10'd1, 32'h8000_0000, 4'h0, 4'hF);
        		  TSK_WAIT_FOR_READ_DATA;
                          if (cpld_to == 1) $display("[%t] : TEST PASSED --- Test correctly timed out. CPLD not received", $realtime);
                          else $display("[%t] : TEST FAILED --- CPLD received", $realtime);
                          $finish; 

                          

		     end
		2'b11 : // MEM 64 SPACE
		     begin

		       $display("[%t] : NOTHING: to Memory 64 Space BAR %x", $realtime, ii);

		   
        	     end
		default : $display("Error case in usrapp_tx\n");
	    endcase
	          
	 end


    $display("[%t] : Finished transmission of PCI-Express TLPs", $realtime);
    $finish;
end


else if(testname == "pio_barRange_Test0")
begin

    // This test will verify the bar range checking ability of the first Mem32 space (not EROM)
    // The first read is valid. The second read is not.

    TSK_SIMULATION_TIMEOUT(10050);

    TSK_SYSTEM_INITIALIZATION;

    TSK_BAR_SCAN;   

    TSK_BUILD_PCIE_MAP; // build the map to determine which spaces are enabled to use in range increasing below
        
    TSK_DISPLAY_PCIE_MAP;
    

	for (ii = 0; ii <= 6; ii = ii + 1) begin  // should go from 0 to 6
	    if (BAR_INIT_P_BAR_ENABLED[ii] > 2'b00) // bar is enabled
               case(BAR_INIT_P_BAR_ENABLED[ii])
		   2'b01 : // IO SPACE
			begin

		        
			   
// future impl. shift over the range to the left one making sure to maintain the io bit

		        end

		   2'b10 : // MEM 32 SPACE
			begin
			

			    temp_register = BAR_INIT_P_BAR_RANGE[ii];
			    // Make the range twice as large so that there will be a hole in the memory map.

			   
// shift over the range to the left one making sure to maintain the prefetchable bit
			   
// and the erom enable bit for ii==6
			   
// for now dont worry about erom
			   
// double the size of the range so that the next build map creates unaddressable

// Memory 32 space

if (ii != 6)

    BAR_INIT_P_BAR_RANGE[ii] = BAR_INIT_P_BAR_RANGE[ii] << 1; // not worrying about prefetch
                            else begin
                               $display("Warning: EROM is only Mem32 space enabled. Ending Simulation");
                               $finish;
                            end


                         // Reset parameters used for determining PCIE MAP
                          BAR_INIT_P_MEM64_HI_START =  32'h0000_0001; // hi 32 bit start of 64bit memory
                          BAR_INIT_P_MEM64_LO_START =  32'h0000_0000; // low 32 bit start of 64bit memory
                          BAR_INIT_P_MEM32_START =     33'h00000_0000; // start of 32bit memory
                          BAR_INIT_P_IO_START      =   33'h00000_0000; // start of 32bit io 
                          pio_check_design = 0; // needed to avoid error checks by testbench

                          TSK_BUILD_PCIE_MAP; // Rebuild PCIE MAP based on increased range
        
                          TSK_DISPLAY_PCIE_MAP;

                          TSK_BAR_PROGRAM;    // Program Chip

		          $display("[%t] : Transmitting TLPs to Memory 32 Space BAR %x", $realtime, ii);

                          temp_register = temp_register ^ BAR_INIT_P_BAR_RANGE[ii][31:0]; // attain the invalid offset
	                  
	                  P_READ_DATA = 32'hffff_ffff; // make sure P_READ_DATA has known initial value
			  // The following read should succeed with cpld
			  // This read is at the top of the BARs range
			  TSK_TX_MEMORY_READ_32(DEFAULT_TAG, DEFAULT_TC, 10'd1, BAR_INIT_P_BAR[ii][31:0]+temp_register-4, 4'h0, 4'hF);
        		  TSK_WAIT_FOR_READ_DATA;
			

                         $display("[%t] : TEST PASSED --- CPLD received", $realtime);

                         

                         // The following read should not succeed with a cpld

                         cpld_to_finish = 0; // Turn off TSK_WAIT_FOR_READ_DATA's finish on timeout default mechanism

                         P_READ_DATA = 32'hffff_ffff; // make sure P_READ_DATA has known initial value 
			  TSK_TX_MEMORY_READ_32(DEFAULT_TAG, DEFAULT_TC, 10'd1, BAR_INIT_P_BAR[ii][31:0]+temp_register, 4'h0, 4'hF);
        		  TSK_WAIT_FOR_READ_DATA;
                          
                          if (cpld_to == 1) $display("[%t] : TEST PASSED --- Test correctly timed out. CPLD not received", $realtime);
                          else $display("[%t] : TEST FAILED --- CPLD received", $realtime);
                           


                       



                        $finish;    


                        
		     end
		   2'b11 : // MEM 64 SPACE 			
		     begin

                           // shift over the range to the left one making sure to maintain the 64 address bit



        	     end
		default : begin
		            $display("Error case in usrapp_tx\n");
		            $finish;
		          end
	    endcase
	          
	 end


end