xilinx_pci_exp_4_lane_ep_inc.xst

基于xilinx vierex5得pci express dma设计实现。

/////////////////////////////////////////////////////////
//     TOP LEVEL FPGA STRUCTURAL NETLIST               //
/////////////////////////////////////////////////////////

`include  "../example_design/xilinx_pci_exp_4_lane_ep_product.v"
`include  "../simulation/xilinx_pci_exp_defines.v"

`include  "../example_design/BMD_64.v"
`include  "../example_design/BMD.v"
`include  "../example_design/BMD_64_RX_ENGINE.v"
`include  "../example_design/BMD_64_TX_ENGINE.v"
`include  "../example_design/BMD_EP.v"
`include  "../example_design/BMD_EP_MEM.v"
`include  "../example_design/BMD_EP_MEM_ACCESS.v"
`include  "../example_design/BMD_INTR_CTRL.v"
`include  "../example_design/BMD_TO_CTRL.v"

`include  "../example_design/xilinx_pci_exp_4_lane_ep.v"
`include  "../example_design/pci_exp_64b_app.v"
//`include  "../example_design/PIO_64.v"
//`include  "../example_design/PIO_EP.v"
//`include  "../example_design/PIO_EP_MEM_ACCESS.v"
//`include  "../example_design/EP_MEM.v"
//`include  "../example_design/PIO_64_RX_ENGINE.v"
//`include  "../example_design/PIO_64_TX_ENGINE.v"
//`include  "../example_design/PIO_TO_CTRL.v"
//`include  "../example_design/PIO.v"



/////////////////////////////////////////////////////////
//     PCI-EXPRESS CORE INSTANCE BLACKBOX              //
/////////////////////////////////////////////////////////

`include  "../example_design/pci_exp_4_lane_64b_ep.v"