xst.srp

基于xilinx vierex5得pci express dma设计实现。

Optimizing unit <BMD_64_TX_ENGINE> ...

Optimizing unit <BMD_EP> ...

Optimizing unit <BMD> ...
WARNING:Xst:2677 - Node <BMD_TO/cfg_turnoff_ok_n> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_TO/trn_pending> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_4> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_5> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_6> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/req_be_o_7> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_7> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_8> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_9> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/addr_o_10> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_4> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_5> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_6> of sequential type is unconnected in block <app/BMD>.
WARNING:Xst:2677 - Node <BMD_EP/EP_RX/wr_be_o_7> of sequential type is unconnected in block <app/BMD>.

Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txn<3>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txn<2>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txn<1>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txn<0>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txp<3>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txp<2>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txp<1>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <pci_exp_txp<0>> driven by black box <endpoint_blk_plus_v1_5>. Possible simulation mismatch.
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 823
 Flip-Flops                                            : 823

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : xilinx_pci_exp_4_lane_ep.ngc
Output Format                      : NGC
Optimization Goal                  : SPEED
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 19

Cell Usage :
# BELS                             : 1753
#      GND                         : 2
#      INV                         : 42
#      LUT1                        : 125
#      LUT2                        : 86
#      LUT3                        : 156
#      LUT4                        : 73
#      LUT5                        : 176
#      LUT6                        : 498
#      MUXCY                       : 270
#      MUXF7                       : 67
#      VCC                         : 2
#      XORCY                       : 256
# FlipFlops/Latches                : 823
#      FDC                         : 339
#      FDCE                        : 443
#      FDE                         : 32
#      FDP                         : 7
#      FDPE                        : 2
# IO Buffers                       : 18
#      IBUF                        : 9
#      IBUFDS                      : 1
#      OBUF                        : 8
# DSPs                             : 1
#      DSP48E                      : 1
# Others                           : 1
#      endpoint_blk_plus_v1_5      : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 5vlx50tff1136-1 


Slice Logic Utilization: 
 Number of Slice Registers:            823  out of  28800     2%  
 Number of Slice LUTs:                1156  out of  28800     4%  
    Number used as Logic:             1156  out of  28800     4%  

Slice Logic Distribution: 
 Number of Bit Slices used:           1476
   Number with an unused Flip Flop     653  out of   1476    44%  
   Number with an unused LUT:          320  out of   1476    21%  
   Number of fully used Bit Slices:    503  out of   1476    34%  
   Number of unique control sets:       25

IO Utilization: 
 Number of IOs:                         19
 Number of bonded IOBs:                 19  out of    480     3%  

Specific Feature Utilization:
 Number of DSP48Es:                      1  out of     48     2%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+--------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                | Load  |
-----------------------------------+--------------------------------------+-------+
trn_clk_c                          | NONE(app/BMD/BMD_EP/EP_TX/trn_tsof_n)| 824   |
-----------------------------------+--------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------------------------------+--------------------------------------+-------+
Control Signal                                                                         | Buffer(FF name)                      | Load  |
---------------------------------------------------------------------------------------+--------------------------------------+-------+
app/BMD/BMD_EP/EP_MEM/EP_MEM/rst_n_inv(app/BMD/BMD_EP/EP_TX/bmd_64_tx_state_Rst_inv1:O)| NONE(app/BMD/BMD_EP/EP_TX/trn_tsof_n)| 791   |
---------------------------------------------------------------------------------------+--------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 3.602ns (Maximum Frequency: 277.624MHz)
   Minimum input arrival time before clock: 4.781ns
   Maximum output required time after clock: 1.370ns
   Maximum combinational path delay: 2.788ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'trn_clk_c'
  Clock period: 3.602ns (frequency: 277.624MHz)
  Total number of paths / destination ports: 17262 / 1228
-------------------------------------------------------------------------
Delay:               3.602ns (Levels of Logic = 8)
  Source:            app/BMD/BMD_EP/EP_TX/cur_wr_count_0 (FF)
  Destination:       app/BMD/BMD_EP/EP_TX/mwr_done_o (FF)
  Source Clock:      trn_clk_c rising
  Destination Clock: trn_clk_c rising

  Data Path: app/BMD/BMD_EP/EP_TX/cur_wr_count_0 to app/BMD/BMD_EP/EP_TX/mwr_done_o
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   0.471   1.085  BMD_EP/EP_TX/cur_wr_count_0 (BMD_EP/EP_TX/cur_wr_count_0)
     LUT6:I0->O            1   0.094   0.000  BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_lut<0> (BMD_EP/EP_TX/N61)
     MUXCY:S->O            1   0.372   0.000  BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<0> (BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<0>)
     MUXCY:CI->O           1   0.026   0.000  BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<1> (BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<1>)
     MUXCY:CI->O           1   0.026   0.000  BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<2> (BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<2>)
     MUXCY:CI->O           1   0.026   0.000  BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<3> (BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<3>)
     MUXCY:CI->O           1   0.026   0.000  BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<4> (BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<4>)
     MUXCY:CI->O          19   0.254   0.579  BMD_EP/EP_TX/Mcompar_mwr_done_o_cmp_ne0000_cy<5> (BMD_EP/EP_TX/mwr_done_o_cmp_ne0000)
     LUT6:I5->O            1   0.094   0.336  BMD_EP/EP_TX/mwr_done_o_not00011 (BMD_EP/EP_TX/mwr_done_o_not0001)
     FDCE:CE                   0.213          BMD_EP/EP_TX/mwr_done_o
    ----------------------------------------
    Total                      3.602ns (1.602ns logic, 2.000ns route)
                                       (44.5% logic, 55.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'trn_clk_c'
  Total number of paths / destination ports: 4942 / 539
-------------------------------------------------------------------------
Offset:              4.781ns (Levels of Logic = 7)
  Source:            ep:trn_rd<59> (PAD)
  Destination:       app/BMD/BMD_EP/EP_RX/cpld_real_size_2 (FF)
  Destination Clock: trn_clk_c rising

  Data Path: ep:trn_rd<59> to app/BMD/BMD_EP/EP_RX/cpld_real_size_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    endpoint_blk_plus_v1_5:trn_rd<59>    2   0.000   0.000  ep (trn_rd_c<59>)
     begin scope: 'app/BMD'
     LUT6:I0->O           19   0.094   0.579  BMD_EP/EP_RX/bmd_64_rx_state_FFd2-In311 (BMD_EP/EP_RX/N431)
     LUT2:I1->O            1   0.094   1.069  BMD_EP/EP_RX/cpld_malformed_o_mux000041_SW0 (N7517)
     LUT6:I0->O            3   0.094   0.491  BMD_EP/EP_RX/cpld_real_size_mux0000<1>211 (BMD_EP/EP_RX/N28)
     LUT5:I4->O            7   0.094   0.513  BMD_EP/EP_RX/cpld_real_size_mux0000<2>31 (BMD_EP/EP_RX/N59)
     LUT5:I4->O            3   0.094   0.491  BMD_EP/EP_RX/cpld_real_size_mux0000<1>_SW0 (N6786)
     LUT6:I5->O            1   0.094   0.000  BMD_EP/EP_RX/cpld_real_size_mux0000<7> (BMD_EP/EP_RX/cpld_real_size_mux0000<7>)
     FDC:D                    -0.018          BMD_EP/EP_RX/cpld_real_size_2
    ----------------------------------------
    Total                      4.781ns (1.638ns logic, 3.143ns route)
                                       (34.3% logic, 65.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'trn_clk_c'
  Total number of paths / destination ports: 83 / 79
-------------------------------------------------------------------------
Offset:              1.370ns (Levels of Logic = 2)
  Source:            app/BMD/BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1 (FF)
  Destination:       ep:cfg_interrupt_n (PAD)
  Source Clock:      trn_clk_c rising

  Data Path: app/BMD/BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1 to ep:cfg_interrupt_n
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.471   0.805  BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1 (BMD_EP/EP_TX/BMD_INTR_CTRL/rd_intr_state_1)
     LUT4:I0->O            0   0.094   0.000  BMD_EP/EP_TX/BMD_INTR_CTRL/cfg_interrupt_n_o1 (cfg_interrupt_n)
     end scope: 'app/BMD'
    endpoint_blk_plus_v1_5:cfg_interrupt_n        0.000          ep
    ----------------------------------------
    Total                      1.370ns (0.565ns logic, 0.805ns route)
                                       (41.2% logic, 58.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 35 / 26
-------------------------------------------------------------------------
Delay:               2.788ns (Levels of Logic = 1)
  Source:            ep:pci_exp_txn<3> (PAD)
  Destination:       pci_exp_txn<3> (PAD)

  Data Path: ep:pci_exp_txn<3> to pci_exp_txn<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    endpoint_blk_plus_v1_5:pci_exp_txn<3>    1   0.000   0.336  ep (pci_exp_txn_3_OBUF)
     OBUF:I->O                 2.452          pci_exp_txn_3_OBUF (pci_exp_txn<3>)
    ----------------------------------------
    Total                      2.788ns (2.452ns logic, 0.336ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX 1": Did not attach to ep.
CPU : 162.69 / 162.75 s | Elapsed : 165.00 / 165.00 s
 
--> 


Total memory usage is 297332 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   86 (   0 filtered)
Number of infos    :    2 (   0 filtered)