xst.srp

基于xilinx vierex5得pci express dma设计实现。

    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst_n (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <mem_wr_data>.
    Found 1-bit register for signal <mem_write_en>.
    Found 32-bit register for signal <pre_wr_data>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  65 D-type flip-flop(s).
Unit <BMD_EP_MEM_ACCESS> synthesized.


Synthesizing Unit <BMD_64_TX_ENGINE>.
    Related source file is "../example_design/BMD_64_TX_ENGINE.v".
WARNING:Xst:647 - Input <mrd_count_i<31:16>> is never used.
WARNING:Xst:647 - Input <req_addr_i<1:0>> is never used.
WARNING:Xst:647 - Input <mwr_tag_i> is never used.
WARNING:Xst:647 - Input <mrd_len_i<31:10>> is never used.
WARNING:Xst:647 - Input <mwr_count_i<31:16>> is never used.
WARNING:Xst:647 - Input <mwr_len_i<31:10>> is never used.
WARNING:Xst:647 - Input <mrd_tag_i> is never used.
WARNING:Xst:647 - Input <req_be_i<7:4>> is never used.
WARNING:Xst:1780 - Signal <tmrd_addr> is never used or assigned.
WARNING:Xst:1780 - Signal <tmwr_addr> is never used or assigned.
    Found finite state machine <FSM_2> for signal <bmd_64_tx_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 48                                             |
    | Inputs             | 14                                             |
    | Outputs            | 9                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst_n (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000001                                        |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 64-bit register for signal <trn_td>.
    Found 1-bit register for signal <mwr_done_o>.
    Found 1-bit register for signal <trn_tsrc_dsc_n>.
    Found 1-bit register for signal <compl_done_o>.
    Found 1-bit register for signal <trn_teof_n>.
    Found 1-bit register for signal <trn_tsrc_rdy_n>.
    Found 1-bit register for signal <trn_tsof_n>.
    Found 8-bit register for signal <trn_trem_n>.
    Found 10-bit register for signal <cur_mwr_dw_count>.
    Found 10-bit subtractor for signal <cur_mwr_dw_count$share0000> created at line 424.
    Found 16-bit register for signal <cur_rd_count>.
    Found 16-bit adder for signal <cur_rd_count$addsub0000> created at line 714.
    Found 1-bit register for signal <cur_rd_not1st>.
    Found 16-bit register for signal <cur_wr_count>.
    Found 16-bit adder for signal <cur_wr_count$addsub0000> created at line 618.
    Found 1-bit register for signal <cur_wr_not1st>.
    Found 1-bit register for signal <mrd_done>.
    Found 16-bit comparator equal for signal <mrd_done$cmp_eq0000> created at line 707.
    Found 16-bit comparator not equal for signal <mrd_done$cmp_ne0000> created at line 707.
    Found 12-bit register for signal <mrd_len_byte>.
    Found 16-bit comparator equal for signal <mwr_done_o$cmp_eq0000> created at line 611.
    Found 16-bit comparator not equal for signal <mwr_done_o$cmp_ne0000> created at line 611.
    Found 12-bit register for signal <mwr_len_byte>.
    Found 32-bit register for signal <pmrd_addr>.
    Found 32-bit adder for signal <pmrd_addr$addsub0000> created at line 702.
    Found 32-bit register for signal <pmwr_addr>.
    Found 32-bit adder for signal <pmwr_addr$addsub0000> created at line 607.
    Found 1-bit register for signal <req_compl_q>.
    Found 16-bit register for signal <rmrd_count>.
    Found 16-bit subtractor for signal <rmrd_count$sub0000> created at line 422.
    Found 16-bit register for signal <rmwr_count>.
    Found 16-bit subtractor for signal <rmwr_count$sub0000> created at line 420.
    Found 1-bit register for signal <serv_mrd>.
    Found 1-bit register for signal <serv_mwr>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 246 D-type flip-flop(s).
	inferred   7 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <BMD_64_TX_ENGINE> synthesized.


Synthesizing Unit <BMD_EP>.
    Related source file is "../example_design/BMD_EP.v".
WARNING:Xst:1780 - Signal <mrd_lbe> is never used or assigned.
WARNING:Xst:1780 - Signal <mrd_tag> is never used or assigned.
WARNING:Xst:1780 - Signal <rd_addr<10:7>> is never used or assigned.
WARNING:Xst:646 - Signal <rd_addr<6:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <mrd_fbe> is never used or assigned.
WARNING:Xst:1780 - Signal <mwr_lbe> is never used or assigned.
WARNING:Xst:1780 - Signal <mwr_tag> is never used or assigned.
WARNING:Xst:1780 - Signal <mwr_fbe> is never used or assigned.
Unit <BMD_EP> synthesized.


Synthesizing Unit <BMD>.
    Related source file is "../example_design/BMD.v".
Unit <BMD> synthesized.


Synthesizing Unit <pci_exp_64b_app>.
    Related source file is "../example_design/pci_exp_64b_app.v".
WARNING:Xst:647 - Input <cfg_dstatus> is never used.
WARNING:Xst:647 - Input <cfg_lcommand> is never used.
WARNING:Xst:647 - Input <trn_rerrfwd_n> is never used.
WARNING:Xst:647 - Input <cfg_status> is never used.
WARNING:Xst:647 - Input <trn_rfc_cplh_av> is never used.
WARNING:Xst:647 - Input <cfg_rd_wr_done_n> is never used.
WARNING:Xst:647 - Input <trn_rfc_nph_av> is never used.
WARNING:Xst:647 - Input <trn_rfc_ph_av> is never used.
WARNING:Xst:647 - Input <trn_tbuf_av> is never used.
WARNING:Xst:647 - Input <trn_rfc_cpld_av> is never used.
WARNING:Xst:647 - Input <cfg_command<15:3>> is never used.
WARNING:Xst:647 - Input <cfg_command<1:0>> is never used.
WARNING:Xst:647 - Input <cfg_lstatus> is never used.
WARNING:Xst:647 - Input <trn_rfc_npd_av> is never used.
WARNING:Xst:647 - Input <trn_rbar_hit_n> is never used.
WARNING:Xst:647 - Input <cfg_dcommand<15>> is never used.
WARNING:Xst:647 - Input <cfg_dcommand<11:9>> is never used.
WARNING:Xst:647 - Input <cfg_dcommand<4:0>> is never used.
WARNING:Xst:647 - Input <cfg_pcie_link_state_n> is never used.
WARNING:Xst:647 - Input <trn_rfc_pd_av> is never used.
WARNING:Xst:647 - Input <cfg_do> is never used.
Unit <pci_exp_64b_app> synthesized.


Synthesizing Unit <xilinx_pci_exp_4_lane_ep>.
    Related source file is "../example_design/xilinx_pci_exp_4_lane_ep.v".
WARNING:Xst:1780 - Signal <cfg_to_turnoff_n> is never used or assigned.
WARNING:Xst:653 - Signal <trn_rfc_cplh_av_c> is used but never assigned. Tied to value 00000000.
WARNING:Xst:653 - Signal <trn_rfc_cpld_av_c> is used but never assigned. Tied to value 000000000000.
WARNING:Xst:646 - Signal <cfg_turnoff_ok_n_c> is assigned but never used.
Unit <xilinx_pci_exp_4_lane_ep> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers                                          : 1
 16x16-bit multiplier                                  : 1
# Adders/Subtractors                                   : 12
 10-bit adder                                          : 2
 10-bit subtractor                                     : 1
 16-bit adder                                          : 2
 16-bit subtractor                                     : 2
 32-bit adder                                          : 4
 8-bit adder                                           : 1
# Counters                                             : 2
 32-bit up counter                                     : 2
# Registers                                            : 68
 1-bit register                                        : 26
 10-bit register                                       : 4
 11-bit register                                       : 1
 12-bit register                                       : 2
 16-bit register                                       : 5
 2-bit register                                        : 1
 21-bit register                                       : 3
 3-bit register                                        : 2
 32-bit register                                       : 15
 6-bit register                                        : 2
 64-bit register                                       : 1
 8-bit register                                        : 6
# Comparators                                          : 6
 10-bit comparator not equal                           : 1
 16-bit comparator equal                               : 2
 16-bit comparator not equal                           : 2
 21-bit comparator equal                               : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <app/BMD/BMD_EP/EP_TX/bmd_64_tx_state> on signal <bmd_64_tx_state[1:3]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 0000001 | 000
 0000010 | 001
 0001000 | 011
 0100000 | 010
 0000100 | 110
 0010000 | 111
---------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <app/BMD/BMD_EP/EP_MEM/wr_mem_state> on signal <wr_mem_state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 010   | 01
 100   | 11
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <app/BMD/BMD_EP/EP_RX/bmd_64_rx_state> on signal <bmd_64_rx_state[1:3]> with sequential encoding.
----------------------
 State    | Encoding
----------------------
 00000001 | 000
 00000010 | 001
 00001000 | 010
 00100000 | 011
 01000000 | 100
 00000100 | 101
 00010000 | 110
 10000000 | 111
----------------------
WARNING:Xst:2404 -  FFs/Latches <req_len_o<9:1>> (without init value) have a constant value of 0 in block <BMD_64_RX_ENGINE>.
WARNING:Xst:2404 -  FFs/Latches <mrd_len_o<31:16>> (without init value) have a constant value of 0 in block <BMD_EP_MEM>.
WARNING:Xst:2404 -  FFs/Latches <mwr_len_o<31:16>> (without init value) have a constant value of 0 in block <BMD_EP_MEM>.
Loading device for application Rf_Device from file '5vlx50t.nph' in environment /program/ise92.

Synthesizing (advanced) Unit <BMD_EP_MEM>.
	Found pipelined multiplier on signal <expect_cpld_data_size_reg_mult0001>:
		- 2 pipeline level(s) found in a register connected to the multiplier macro output.
		Pushing register(s) into the multiplier macro.
Unit <BMD_EP_MEM> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 3
# Multipliers                                          : 1
 16x16-bit registered multiplier                       : 1
# Adders/Subtractors                                   : 12
 10-bit adder                                          : 2
 10-bit subtractor                                     : 1
 16-bit adder                                          : 2
 16-bit subtractor                                     : 2
 32-bit adder                                          : 4
 8-bit adder                                           : 1
# Counters                                             : 2
 32-bit up counter                                     : 2
# Registers                                            : 781
 Flip-Flops                                            : 781
# Comparators                                          : 6
 10-bit comparator not equal                           : 1
 16-bit comparator equal                               : 2
 16-bit comparator not equal                           : 2
 21-bit comparator equal                               : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <mwr_len_byte_0> (without init value) has a constant value of 0 in block <BMD_64_TX_ENGINE>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <mwr_len_byte_1> (without init value) has a constant value of 0 in block <BMD_64_TX_ENGINE>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <mrd_len_byte_0> (without init value) has a constant value of 0 in block <BMD_64_TX_ENGINE>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <mrd_len_byte_1> (without init value) has a constant value of 0 in block <BMD_64_TX_ENGINE>.
WARNING:Xst:2677 - Node <pmrd_addr_0> of sequential type is unconnected in block <BMD_64_TX_ENGINE>.
WARNING:Xst:2677 - Node <pmrd_addr_1> of sequential type is unconnected in block <BMD_64_TX_ENGINE>.
WARNING:Xst:2677 - Node <pmwr_addr_0> of sequential type is unconnected in block <BMD_64_TX_ENGINE>.
WARNING:Xst:2677 - Node <pmwr_addr_1> of sequential type is unconnected in block <BMD_64_TX_ENGINE>.

Optimizing unit <xilinx_pci_exp_4_lane_ep> ...

Optimizing unit <BMD_TO_CTRL> ...

Optimizing unit <BMD_64_RX_ENGINE> ...

Optimizing unit <BMD_EP_MEM> ...

Optimizing unit <BMD_INTR_CTRL> ...

Optimizing unit <BMD_EP_MEM_ACCESS> ...