xst.srp

基于xilinx vierex5得pci express dma设计实现。

Release 9.2.03i - xst J.39
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "xilinx_pci_exp_4_lane_ep_inc.xst"
Input Format                       : Verilog

---- Target Parameters
Target Device                      : xc5vlx50t-ff1136-1
Output File Name                   : "xilinx_pci_exp_4_lane_ep.ngc"
Output Format                      : NGC

---- Source Options
Top Module Name                    : xilinx_pci_exp_4_lane_ep

---- Target Options
Add Generic Clock Buffer(BUFG)     : 0

---- General Options
Optimization Goal                  : SPEED
Optimization Effort                : 2

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "xilinx_pci_exp_4_lane_ep_inc.xst" in library work
Compiling verilog include file "../example_design/xilinx_pci_exp_4_lane_ep_product.v"
Compiling verilog include file "../simulation/xilinx_pci_exp_defines.v"
Compiling verilog include file "../example_design/BMD_64.v"
Compiling verilog include file "../example_design/BMD.v"
Compiling verilog include file "../example_design/BMD_64_RX_ENGINE.v"
Module <BMD> compiled
Compiling verilog include file "../example_design/BMD_64_TX_ENGINE.v"
Module <BMD_64_RX_ENGINE> compiled
Compiling verilog include file "../example_design/BMD_EP.v"
Module <BMD_64_TX_ENGINE> compiled
Compiling verilog include file "../example_design/BMD_EP_MEM.v"
Module <BMD_EP> compiled
Compiling verilog include file "../example_design/BMD_EP_MEM_ACCESS.v"
Module <BMD_EP_MEM> compiled
Compiling verilog include file "../example_design/BMD_INTR_CTRL.v"
Module <BMD_EP_MEM_ACCESS> compiled
Compiling verilog include file "../example_design/BMD_TO_CTRL.v"
Module <BMD_INTR_CTRL> compiled
Compiling verilog include file "../example_design/xilinx_pci_exp_4_lane_ep.v"
Module <BMD_TO_CTRL> compiled
Compiling verilog include file "../example_design/pci_exp_64b_app.v"
Module <xilinx_pci_exp_4_lane_ep> compiled
Compiling verilog include file "../example_design/pci_exp_4_lane_64b_ep.v"
Module <pci_exp_64b_app> compiled
Module <endpoint_blk_plus_v1_5> compiled
No errors in compilation
Analysis of file <"xilinx_pci_exp_4_lane_ep_inc.xst"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <xilinx_pci_exp_4_lane_ep> in library <work>.

Analyzing hierarchy for module <pci_exp_64b_app> in library <work>.

Analyzing hierarchy for module <BMD> in library <work>.

Analyzing hierarchy for module <BMD_EP> in library <work>.

Analyzing hierarchy for module <BMD_TO_CTRL> in library <work>.

Analyzing hierarchy for module <BMD_EP_MEM_ACCESS> in library <work>.

Analyzing hierarchy for module <BMD_64_RX_ENGINE> in library <work>.

Analyzing hierarchy for module <BMD_64_TX_ENGINE> in library <work>.

Analyzing hierarchy for module <BMD_EP_MEM> in library <work>.

Analyzing hierarchy for module <BMD_INTR_CTRL> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <xilinx_pci_exp_4_lane_ep>.
WARNING:Xst:2211 - "../example_design/pci_exp_4_lane_64b_ep.v" line 249: Instantiating black box module <endpoint_blk_plus_v1_5>.
Module <xilinx_pci_exp_4_lane_ep> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <refclk_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <refclk_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <refclk_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <refclk_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <refclk_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <sys_reset_n_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <sys_reset_n_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <sys_reset_n_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <sys_reset_n_ibuf> in unit <xilinx_pci_exp_4_lane_ep>.
    Set user-defined property "SYN_BLACK_BOX =  1" for instance <ep> in unit <xilinx_pci_exp_4_lane_ep>.
WARNING:Xst:39 - Property "buffer_type" not applicable on a entity.
    Set property "max_fanout = 100000" for signal <trn_clk_c>.
Analyzing module <pci_exp_64b_app> in library <work>.
Module <pci_exp_64b_app> is correct for synthesis.
 
Analyzing module <BMD> in library <work>.
Module <BMD> is correct for synthesis.
 
    Set property "SYN_HIER = hard" for unit <BMD>.
Analyzing module <BMD_EP> in library <work>.
Module <BMD_EP> is correct for synthesis.
 
Analyzing module <BMD_EP_MEM_ACCESS> in library <work>.
Module <BMD_EP_MEM_ACCESS> is correct for synthesis.
 
Analyzing module <BMD_EP_MEM> in library <work>.
Module <BMD_EP_MEM> is correct for synthesis.
 
Analyzing module <BMD_64_RX_ENGINE> in library <work>.
Module <BMD_64_RX_ENGINE> is correct for synthesis.
 
Analyzing module <BMD_64_TX_ENGINE> in library <work>.
Module <BMD_64_TX_ENGINE> is correct for synthesis.
 
Analyzing module <BMD_INTR_CTRL> in library <work>.
"../example_design/BMD_INTR_CTRL.v" line 124: Found Full Case directive in module <BMD_INTR_CTRL>.
"../example_design/BMD_INTR_CTRL.v" line 196: Found Full Case directive in module <BMD_INTR_CTRL>.
"../example_design/BMD_INTR_CTRL.v" line 275: Found Full Case directive in module <BMD_INTR_CTRL>.
Module <BMD_INTR_CTRL> is correct for synthesis.
 
Analyzing module <BMD_TO_CTRL> in library <work>.
Module <BMD_TO_CTRL> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <BMD_TO_CTRL>.
    Related source file is "../example_design/BMD_TO_CTRL.v".
    Found 1-bit register for signal <cfg_turnoff_ok_n>.
    Found 1-bit register for signal <trn_pending>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <BMD_TO_CTRL> synthesized.


Synthesizing Unit <BMD_64_RX_ENGINE>.
    Related source file is "../example_design/BMD_64_RX_ENGINE.v".
WARNING:Xst:647 - Input <trn_rsrc_dsc_n> is never used.
    Found finite state machine <FSM_0> for signal <bmd_64_rx_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 39                                             |
    | Inputs             | 15                                             |
    | Outputs            | 11                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst_n (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00000001                                       |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <cpld_data_size_o>.
    Found 16-bit register for signal <req_rid_o>.
    Found 8-bit register for signal <cpl_ur_found_o>.
    Found 32-bit register for signal <wr_data_o>.
    Found 11-bit register for signal <addr_o>.
    Found 1-bit register for signal <req_ep_o>.
    Found 3-bit register for signal <req_tc_o>.
    Found 2-bit register for signal <req_attr_o>.
    Found 8-bit register for signal <wr_be_o>.
    Found 10-bit register for signal <req_len_o>.
    Found 1-bit register for signal <req_td_o>.
    Found 1-bit register for signal <wr_en_o>.
    Found 32-bit register for signal <cpld_found_o>.
    Found 1-bit register for signal <trn_rdst_rdy_n>.
    Found 1-bit register for signal <req_compl_o>.
    Found 8-bit register for signal <req_tag_o>.
    Found 8-bit register for signal <cpl_ur_tag_o>.
    Found 1-bit register for signal <cpld_malformed_o>.
    Found 8-bit register for signal <req_be_o>.
    Found 8-bit adder for signal <cpl_ur_found_o$addsub0000> created at line 290.
    Found 32-bit adder for signal <cpld_data_size_o$addsub0000> created at line 300.
    Found 32-bit adder for signal <cpld_found_o$addsub0000> created at line 302.
    Found 10-bit adder for signal <cpld_malformed_o$add0000> created at line 426.
    Found 10-bit comparator not equal for signal <cpld_malformed_o$cmp_ne0001> created at line 426.
    Found 10-bit register for signal <cpld_real_size>.
    Found 10-bit adder for signal <cpld_real_size$addsub0000> created at line 438.
    Found 10-bit register for signal <cpld_tlp_size>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 204 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <BMD_64_RX_ENGINE> synthesized.


Synthesizing Unit <BMD_EP_MEM>.
    Related source file is "../example_design/BMD_EP_MEM.v".
WARNING:Xst:643 - "../example_design/BMD_EP_MEM.v" line 388: The result of a 16x16-bit multiplication is partially used. Only the 21 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 32-bit register for signal <mrd_count_o>.
    Found 32-bit register for signal <rd_d_o>.
    Found 32-bit register for signal <mwr_addr_o>.
    Found 32-bit register for signal <mwr_data_o>.
    Found 1-bit register for signal <mrd_start_o>.
    Found 1-bit register for signal <mrd_done_o>.
    Found 32-bit register for signal <mrd_addr_o>.
    Found 32-bit register for signal <mrd_len_o>.
    Found 1-bit register for signal <init_rst_o>.
    Found 32-bit register for signal <mwr_count_o>.
    Found 1-bit register for signal <mwr_start_o>.
    Found 32-bit register for signal <mwr_len_o>.
    Found 21-bit register for signal <cpld_data_size>.
    Found 1-bit register for signal <cpld_done>.
    Found 21-bit comparator equal for signal <cpld_done$cmp_eq0000> created at line 411.
    Found 21-bit register for signal <expect_cpld_data_size>.
    Found 21-bit register for signal <expect_cpld_data_size_reg>.
    Found 32-bit up counter for signal <mrd_perf>.
    Found 32-bit up counter for signal <mwr_perf>.
    Summary:
	inferred   2 Counter(s).
	inferred 324 D-type flip-flop(s).
	inferred   1 Multiplier(s).
	inferred   1 Comparator(s).
Unit <BMD_EP_MEM> synthesized.


Synthesizing Unit <BMD_INTR_CTRL>.
    Related source file is "../example_design/BMD_INTR_CTRL.v".
WARNING:Xst:647 - Input <cfg_interrupt_mmenable_i> is never used.
WARNING:Xst:1780 - Signal <cfg_interrupt_assert_n_wr> is never used or assigned.
WARNING:Xst:1780 - Signal <cfg_interrupt_assert_n_rd> is never used or assigned.
    Using one-hot encoding for signal <intr_state>.
    Using one-hot encoding for signal <wr_intr_state>.
    Using one-hot encoding for signal <rd_intr_state>.
    Found 3-bit register for signal <intr_state>.
    Found 6-bit register for signal <rd_intr_state>.
    Found 6-bit register for signal <wr_intr_state>.
Unit <BMD_INTR_CTRL> synthesized.


Synthesizing Unit <BMD_EP_MEM_ACCESS>.
    Related source file is "../example_design/BMD_EP_MEM_ACCESS.v".
WARNING:Xst:647 - Input <wr_be_i<7:4>> is never used.
WARNING:Xst:1780 - Signal <w_pre_wr_data> is never used or assigned.
    Found finite state machine <FSM_1> for signal <wr_mem_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 4                                              |
    | Inputs             | 1                                              |