routed.bgn

基于xilinx vierex5得pci express dma设计实现。

Release 9.2.03i - Bitgen J.39
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '5vlx50t.nph' in environment
/program/ise92.
   "xilinx_pci_exp_4_lane_ep" is an NCD, version 3.1, device xc5vlx50t, package
ff1136, speed -1

Sun Dec  2 17:43:00 2007

bitgen -w routed.ncd 

Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable*              |
+----------------------+----------------------+
| DebugBitstream       | No*                  |
+----------------------+----------------------+
| ConfigRate           | 2*                   |
+----------------------+----------------------+
| StartupClk           | Cclk*                |
+----------------------+----------------------+
| CclkPin              | Pullup*              |
+----------------------+----------------------+
| DonePin              | Pullup*              |
+----------------------+----------------------+
| HswapenPin           | Pullup*              |
+----------------------+----------------------+
| M0Pin                | Pullup*              |
+----------------------+----------------------+
| M1Pin                | Pullup*              |
+----------------------+----------------------+
| M2Pin                | Pullup*              |
+----------------------+----------------------+
| ProgPin              | Pullup*              |
+----------------------+----------------------+
| InitPin              | Pullup*              |
+----------------------+----------------------+
| CsPin                | Pullup*              |
+----------------------+----------------------+
| DinPin               | Pullup*              |
+----------------------+----------------------+
| BusyPin              | Pullup*              |
+----------------------+----------------------+
| RdWrPin              | Pullup*              |
+----------------------+----------------------+
| TckPin               | Pullup*              |
+----------------------+----------------------+
| TdiPin               | Pullup*              |
+----------------------+----------------------+
| TdoPin               | Pullup*              |
+----------------------+----------------------+
| TmsPin               | Pullup*              |
+----------------------+----------------------+
| UnusedPin            | Pulldown*            |
+----------------------+----------------------+
| GWE_cycle            | 6*                   |
+----------------------+----------------------+
| GTS_cycle            | 5*                   |
+----------------------+----------------------+
| OverTempPowerDown    | Disable*             |
+----------------------+----------------------+
| LCK_cycle            | NoWait*              |
+----------------------+----------------------+
| Match_cycle          | Auto*                |
+----------------------+----------------------+
| DONE_cycle           | 4*                   |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No*                  |
+----------------------+----------------------+
| DonePipe             | No*                  |
+----------------------+----------------------+
| Security             | None*                |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF*          |
+----------------------+----------------------+
| ActivateGclk         | No*                  |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| Encrypt              | No*                  |
+----------------------+----------------------+
| Key0                 | pick*                |
+----------------------+----------------------+
| StartCBC             | pick*                |
+----------------------+----------------------+
| KeyFile              | (Not Specified)*     |
+----------------------+----------------------+
| DCIUpdateMode        | AsRequired*          |
+----------------------+----------------------+
| ConfigFallback       | Enable*              |
+----------------------+----------------------+
| SelectMAPAbort       | Enable*              |
+----------------------+----------------------+
| RetainConfigStatus   | Yes*                 |
+----------------------+----------------------+
| BPI_page_size        | 1*                   |
+----------------------+----------------------+
| BPI_1st_read_cycle   | 1*                   |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No*                  |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<2> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<3> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<1> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 4 warnings.
Creating bit map...
Saving bit stream in "routed.bit".
Bitstream generation is complete.