decoder_tb.v

MIPS CPU tested in Icarus Verilog

`include "decoder.v"

module decodit();

   // Declare inputs as regs and outputs as wires
   reg Clock;
   reg [31:0] Instruction;
   wire       Branch;
   wire       Jump;
   wire       Write_RF;
   wire       Src2;
   wire [5:0] ALUOP;
   wire [1:0] RegDest;
   wire       Memory_Read;
   wire       Memory_Write;
   wire [2:0] Mem2Reg;
   wire       IntFP;
   wire       ArSh;

   // Initialize all variables
   initial begin
	  // Add VCD file parameters, dump ALL variables
	  $dumpfile ("decodi_tb1.vcd");
	  $dumpvars;
	  
	  $display ("time\t Clock Instruction Branch Jump Write_RF Src2 ALUOP RegDest Memory_Read Memory_Write Mem2Reg IntFP ArSh");	
	  $monitor ("%g\t %b  %b  %b  %b  %b   %b   %b  %b  %b  %b  %b %b %b", 
				$time, Clock, Instruction, Branch, Jump, Write_RF, Src2, ALUOP, RegDest, Memory_Read, Memory_Write, Mem2Reg, IntFP, ArSh);	
	  Clock = 1;       // initial value of clock
//	  reset = 0;       // initial value of reset
//	  ent = 0;
	  
	  #2 Instruction=32'b00100000000000000000000000000000;
	  #2 Instruction=32'b00100100000000000000000000000000;
	  #2 Instruction=32'b00110000000000000000000000000000;
	  #2 Instruction=32'b00110100000000000000000000000000;
	  #2 Instruction=32'b00111000000000000000000000000000;


	  #2 Instruction=32'b00000000000000000000000000100000;
	  #2 Instruction=32'b00000000000000000000000000100001;
	  #2 Instruction=32'b00000000000000000000000000100010;
	  #2 Instruction=32'b00000000000000000000000000100011;
	  #2 Instruction=32'b00000000000000000000000000100100;
	  #2 Instruction=32'b00000000000000000000000000100110;
	  #2 Instruction=32'b00000000000000000000000000100111;

	  #2 Instruction=32'b00000000000000000000000000000000;
	  #2 Instruction=32'b00000000000000000000000000000010;
	  #2 Instruction=32'b00000000000000000000000000000011;

	  #2 Instruction=32'b00000000000000000000000000000100;
	  #2 Instruction=32'b00000000000000000000000000000110;
	  #2 Instruction=32'b00000000000000000000000000000111;

	  #2 Instruction=32'b01000100000000000000000000000101;
	  #2 Instruction=32'b01000100000000000000000000000000;
	  #2 Instruction=32'b01000100000000000000000000000011;
	  #2 Instruction=32'b01000100000000000000000000000010;
	  #2 Instruction=32'b01000100000000000000000000000111;
	  #2 Instruction=32'b01000100000000000000000000000001;




	  #4 $finish;     // Terminate simulation
   end
   
   // Clock generator
   always begin
	  #1 Clock = ~Clock; // Toggle clock every 1 tick
   end
   
   // Connect DUT to test bench
   decoder U_decodi_tb (

  Clock,
  Instruction,
  Branch,
  Jump,
  Write_RF,
  Src2,
  ALUOP,
  RegDest,
  Memory_Read,
  Memory_Write,
  Mem2Reg,
  IntFP,
  ArSh);
   
endmodule