freqm.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 15 行 · 第 1/5 页

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "divider2:inst1\|oCLK counter:inst14\|C CLK 37.0 ns " "Info: Found hold time violation between source  pin or register divider2:inst1\|oCLK and destination pin or register counter:inst14\|C for clock CLK (Hold time is 37.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "42.000 ns + Largest " "Info: + Largest clock skew is 42.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 54.000 ns + Longest register " "Info: + Longest clock path from clock CLK to destination register is 54.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 12 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -152 -392 -224 -136 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(8.000 ns) 12.000 ns selector:inst16\|Pulse~26 2 COMB SEXP70 3 " "Info: 2: + IC(1.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP70; Fanout = 3; COMB Node = 'selector:inst16\|Pulse~26'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { CLK selector:inst16|Pulse~26 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 19.000 ns counter:inst10\|C 3 REG LC68 9 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC68; Fanout = 9; REG Node = 'counter:inst10\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "7.000 ns" { selector:inst16|Pulse~26 counter:inst10|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 28.000 ns counter:inst11\|C 4 REG LC66 9 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC66; Fanout = 9; REG Node = 'counter:inst11\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst10|C counter:inst11|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 37.000 ns counter:inst12\|C 5 REG LC100 9 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 37.000 ns; Loc. = LC100; Fanout = 9; REG Node = 'counter:inst12\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst11|C counter:inst12|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 46.000 ns counter:inst13\|C 6 REG LC98 9 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 46.000 ns; Loc. = LC98; Fanout = 9; REG Node = 'counter:inst13\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst12|C counter:inst13|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 54.000 ns counter:inst14\|C 7 REG LC55 8 " "Info: 7: + IC(2.000 ns) + CELL(6.000 ns) = 54.000 ns; Loc. = LC55; Fanout = 8; REG Node = 'counter:inst14\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst13|C counter:inst14|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "45.000 ns 83.33 % " "Info: Total cell delay = 45.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.000 ns 16.67 % " "Info: Total interconnect delay = 9.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "54.000 ns" { CLK selector:inst16|Pulse~26 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 12.000 ns - Shortest register " "Info: - Shortest clock path from clock CLK to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 12 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -152 -392 -224 -136 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns divider1000:inst2\|clk_o 2 REG LC125 15 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC125; Fanout = 15; REG Node = 'divider1000:inst2\|clk_o'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "1.000 ns" { CLK divider1000:inst2|clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider1000.vhd" "" "" { Text "D:/051750/freqm/divider1000.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns divider2:inst1\|oCLK 3 REG LC81 15 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC81; Fanout = 15; REG Node = 'divider2:inst1\|oCLK'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { divider1000:inst2|clk_o divider2:inst1|oCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider2.vhd" "" "" { Text "D:/051750/freqm/divider2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "12.000 ns" { CLK divider1000:inst2|clk_o divider2:inst1|oCLK } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "54.000 ns" { CLK selector:inst16|Pulse~26 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "12.000 ns" { CLK divider1000:inst2|clk_o divider2:inst1|oCLK } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/divider2.vhd" "" "" { Text "D:/051750/freqm/divider2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns - Shortest register register " "Info: - Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divider2:inst1\|oCLK 1 REG LC81 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC81; Fanout = 15; REG Node = 'divider2:inst1\|oCLK'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { divider2:inst1|oCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider2.vhd" "" "" { Text "D:/051750/freqm/divider2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns counter:inst14\|C 2 REG LC55 8 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC55; Fanout = 8; REG Node = 'counter:inst14\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { divider2:inst1|oCLK counter:inst14|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { divider2:inst1|oCLK counter:inst14|C } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "54.000 ns" { CLK selector:inst16|Pulse~26 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "12.000 ns" { CLK divider1000:inst2|clk_o divider2:inst1|oCLK } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { divider2:inst1|oCLK counter:inst14|C } "NODE_NAME" } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "SIGNAL 9 " "Warning: Circuit may not operate. Detected 9 non-operational path(s) clocked by clock SIGNAL with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "selector:inst16\|SIG2 counter:inst14\|C SIGNAL 39.0 ns " "Info: Found hold time violation between source  pin or register selector:inst16\|SIG2 and destination pin or register counter:inst14\|C for clock SIGNAL (Hold time is 39.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "44.000 ns + Largest " "Info: + Largest clock skew is 44.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SIGNAL destination 54.000 ns + Longest register " "Info: + Longest clock path from clock SIGNAL to destination register is 54.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SIGNAL 1 CLK PIN_22 18 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_22; Fanout = 18; CLK Node = 'SIGNAL'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { SIGNAL } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -24 -72 96 -8 "SIGNAL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns selector:inst16\|Pulse~25 2 COMB SEXP71 3 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP71; Fanout = 3; COMB Node = 'selector:inst16\|Pulse~25'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "10.000 ns" { SIGNAL selector:inst16|Pulse~25 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 19.000 ns counter:inst10\|C 3 REG LC68 9 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC68; Fanout = 9; REG Node = 'counter:inst10\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "7.000 ns" { selector:inst16|Pulse~25 counter:inst10|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 28.000 ns counter:inst11\|C 4 REG LC66 9 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC66; Fanout = 9; REG Node = 'counter:inst11\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst10|C counter:inst11|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 37.000 ns counter:inst12\|C 5 REG LC100 9 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 37.000 ns; Loc. = LC100; Fanout = 9; REG Node = 'counter:inst12\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst11|C counter:inst12|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 46.000 ns counter:inst13\|C 6 REG LC98 9 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 46.000 ns; Loc. = LC98; Fanout = 9; R