freqm.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 15 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SWITCH\[0\] register counter:inst15\|cntbuf\[3\] register counter:inst15\|COUNT\[3\] 17.24 MHz 58.0 ns Internal " "Info: Clock SWITCH\[0\] has Internal fmax of 17.24 MHz between source register counter:inst15\|cntbuf\[3\] and destination register counter:inst15\|COUNT\[3\] (period= 58.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst15\|cntbuf\[3\] 1 REG LC1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'counter:inst15\|cntbuf\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { counter:inst15|cntbuf[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns counter:inst15\|COUNT\[3\] 2 REG LC7 9 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC7; Fanout = 9; REG Node = 'counter:inst15\|COUNT\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-45.000 ns - Smallest " "Info: - Smallest clock skew is -45.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SWITCH\[0\] destination 18.000 ns + Shortest register " "Info: + Shortest clock path from clock SWITCH\[0\] to destination register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SWITCH\[0\] 1 CLK PIN_54 49 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 49; CLK Node = 'SWITCH\[0\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { SWITCH[0] } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -8 -72 96 8 "SWITCH\[1..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns selector:inst16\|En~340 2 COMB SEXP3 12 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP3; Fanout = 12; COMB Node = 'selector:inst16\|En~340'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "10.000 ns" { SWITCH[0] selector:inst16|En~340 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns counter:inst15\|COUNT\[3\] 3 REG LC7 9 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC7; Fanout = 9; REG Node = 'counter:inst15\|COUNT\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "6.000 ns" { selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 88.89 % " "Info: Total cell delay = 16.000 ns ( 88.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 11.11 % " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "18.000 ns" { SWITCH[0] selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SWITCH\[0\] source 63.000 ns - Longest register " "Info: - Longest clock path from clock SWITCH\[0\] to source register is 63.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SWITCH\[0\] 1 CLK PIN_54 49 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 49; CLK Node = 'SWITCH\[0\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { SWITCH[0] } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -8 -72 96 8 "SWITCH\[1..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns selector:inst16\|Pulse~25 2 COMB SEXP71 3 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP71; Fanout = 3; COMB Node = 'selector:inst16\|Pulse~25'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "10.000 ns" { SWITCH[0] selector:inst16|Pulse~25 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 19.000 ns counter:inst10\|C 3 REG LC68 9 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC68; Fanout = 9; REG Node = 'counter:inst10\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "7.000 ns" { selector:inst16|Pulse~25 counter:inst10|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 28.000 ns counter:inst11\|C 4 REG LC66 9 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC66; Fanout = 9; REG Node = 'counter:inst11\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst10|C counter:inst11|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 37.000 ns counter:inst12\|C 5 REG LC100 9 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 37.000 ns; Loc. = LC100; Fanout = 9; REG Node = 'counter:inst12\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst11|C counter:inst12|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 46.000 ns counter:inst13\|C 6 REG LC98 9 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 46.000 ns; Loc. = LC98; Fanout = 9; REG Node = 'counter:inst13\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst12|C counter:inst13|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 55.000 ns counter:inst14\|C 7 REG LC55 8 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 55.000 ns; Loc. = LC55; Fanout = 8; REG Node = 'counter:inst14\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst13|C counter:inst14|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 63.000 ns counter:inst15\|cntbuf\[3\] 8 REG LC1 4 " "Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 63.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'counter:inst15\|cntbuf\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "51.000 ns 80.95 % " "Info: Total cell delay = 51.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.000 ns 19.05 % " "Info: Total interconnect delay = 12.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { SWITCH[0] selector:inst16|Pulse~25 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "18.000 ns" { SWITCH[0] selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { SWITCH[0] selector:inst16|Pulse~25 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "18.000 ns" { SWITCH[0] selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { SWITCH[0] selector:inst16|Pulse~25 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "SWITCH\[1\] " "Info: No valid register-to-register paths exist for clock SWITCH\[1\]" {  } {  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 9 " "Warning: Circuit may not operate. Detected 9 non-operational path(s) clocked by clock CLK with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}