freqm.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 15 行 · 第 1/5 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "27 " "Warning: Found 27 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter:inst14\|C " "Info: Detected ripple clock counter:inst14\|C as buffer" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "counter:inst14\|C" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~348 " "Info: Detected gated clock selector:inst16\|En~348 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~348" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~347 " "Info: Detected gated clock selector:inst16\|En~347 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~347" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~346 " "Info: Detected gated clock selector:inst16\|En~346 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~346" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst13\|C " "Info: Detected ripple clock counter:inst13\|C as buffer" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "counter:inst13\|C" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst12\|C " "Info: Detected ripple clock counter:inst12\|C as buffer" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "counter:inst12\|C" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~345 " "Info: Detected gated clock selector:inst16\|En~345 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~345" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~344 " "Info: Detected gated clock selector:inst16\|En~344 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~344" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~343 " "Info: Detected gated clock selector:inst16\|En~343 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~343" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~342 " "Info: Detected gated clock selector:inst16\|En~342 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~342" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~341 " "Info: Detected gated clock selector:inst16\|En~341 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~341" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~340 " "Info: Detected gated clock selector:inst16\|En~340 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~340" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst11\|C " "Info: Detected ripple clock counter:inst11\|C as buffer" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "counter:inst11\|C" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst10\|C " "Info: Detected ripple clock counter:inst10\|C as buffer" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "counter:inst10\|C" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|Pulse~26 " "Info: Detected gated clock selector:inst16\|Pulse~26 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|Pulse~26" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|Pulse~25 " "Info: Detected gated clock selector:inst16\|Pulse~25 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|Pulse~25" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~339 " "Info: Detected gated clock selector:inst16\|En~339 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~339" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~338 " "Info: Detected gated clock selector:inst16\|En~338 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~338" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~337 " "Info: Detected gated clock selector:inst16\|En~337 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~337" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|Pulse~16 " "Info: Detected gated clock selector:inst16\|Pulse~16 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|Pulse~16" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|Pulse~15 " "Info: Detected gated clock selector:inst16\|Pulse~15 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|Pulse~15" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~195 " "Info: Detected gated clock selector:inst16\|En~195 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~195" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~194 " "Info: Detected gated clock selector:inst16\|En~194 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~194" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "selector:inst16\|En~193 " "Info: Detected gated clock selector:inst16\|En~193 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|En~193" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "divider2:inst1\|oCLK " "Info: Detected ripple clock divider2:inst1\|oCLK as buffer" {  } { { "D:/051750/freqm/divider2.vhd" "" "" { Text "D:/051750/freqm/divider2.vhd" 6 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "divider2:inst1\|oCLK" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "divider1000:inst2\|clk_o " "Info: Detected ripple clock divider1000:inst2\|clk_o as buffer" {  } { { "D:/051750/freqm/divider1000.vhd" "" "" { Text "D:/051750/freqm/divider1000.vhd" 16 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "divider1000:inst2\|clk_o" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "selector:inst16\|SIG2 " "Info: Detected ripple clock selector:inst16\|SIG2 as buffer" {  } { { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 27 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "selector:inst16\|SIG2" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register counter:inst15\|cntbuf\[3\] register counter:inst15\|COUNT\[3\] 21.28 MHz 47.0 ns Internal " "Info: Clock CLK has Internal fmax of 21.28 MHz between source register counter:inst15\|cntbuf\[3\] and destination register counter:inst15\|COUNT\[3\] (period= 47.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst15\|cntbuf\[3\] 1 REG LC1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'counter:inst15\|cntbuf\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { counter:inst15|cntbuf[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns counter:inst15\|COUNT\[3\] 2 REG LC7 9 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC7; Fanout = 9; REG Node = 'counter:inst15\|COUNT\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-34.000 ns - Smallest " "Info: - Smallest clock skew is -34.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 29.000 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 29.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 12 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -152 -392 -224 -136 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns divider1000:inst2\|clk_o 2 REG LC125 15 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC125; Fanout = 15; REG Node = 'divider1000:inst2\|clk_o'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "1.000 ns" { CLK divider1000:inst2|clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider1000.vhd" "" "" { Text "D:/051750/freqm/divider1000.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns divider2:inst1\|oCLK 3 REG LC81 15 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC81; Fanout = 15; REG Node = 'divider2:inst1\|oCLK'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { divider1000:inst2|clk_o divider2:inst1|oCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider2.vhd" "" "" { Text "D:/051750/freqm/divider2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 23.000 ns selector:inst16\|En~340 4 COMB SEXP3 12 " "Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 23.000 ns; Loc. = SEXP3; Fanout = 12; COMB Node = 'selector:inst16\|En~340'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "10.000 ns" { divider2:inst1|oCLK selector:inst16|En~340 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 29.000 ns counter:inst15\|COUNT\[3\] 5 REG LC7 9 " "Info: 5: + IC(0.000 ns) + CELL(6.000 ns) = 29.000 ns; Loc. = LC7; Fanout = 9; REG Node = 'counter:inst15\|COUNT\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "6.000 ns" { selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.000 ns 86.21 % " "Info: Total cell delay = 25.000 ns ( 86.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 13.79 % " "Info: Total interconnect delay = 4.000 ns ( 13.79 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "29.000 ns" { CLK divider1000:inst2|clk_o divider2:inst1|oCLK selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 63.000 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 63.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 12 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -152 -392 -224 -136 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(8.000 ns) 12.000 ns selector:inst16\|Pulse~26 2 COMB SEXP70 3 " "Info: 2: + IC(1.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP70; Fanout = 3; COMB Node = 'selector:inst16\|Pulse~26'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { CLK selector:inst16|Pulse~26 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 19.000 ns counter:inst10\|C 3 REG LC68 9 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC68; Fanout = 9; REG Node = 'counter:inst10\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "7.000 ns" { selector:inst16|Pulse~26 counter:inst10|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 28.000 ns counter:inst11\|C 4 REG LC66 9 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC66; Fanout = 9; REG Node = 'counter:inst11\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst10|C counter:inst11|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 37.000 ns counter:inst12\|C 5 REG LC100 9 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 37.000 ns; Loc. = LC100; Fanout = 9; REG Node = 'counter:inst12\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst11|C counter:inst12|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 46.000 ns counter:inst13\|C 6 REG LC98 9 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 46.000 ns; Loc. = LC98; Fanout = 9; REG Node = 'counter:inst13\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst12|C counter:inst13|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 55.000 ns counter:inst14\|C 7 REG LC55 8 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 55.000 ns; Loc. = LC55; Fanout = 8; REG Node = 'counter:inst14\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst13|C counter:inst14|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 63.000 ns counter:inst15\|cntbuf\[3\] 8 REG LC1 4 " "Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 63.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'counter:inst15\|cntbuf\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "52.000 ns 82.54 % " "Info: Total cell delay = 52.000 ns ( 82.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.000 ns 17.46 % " "Info: Total interconnect delay = 11.000 ns ( 17.46 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { CLK selector:inst16|Pulse~26 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "29.000 ns" { CLK divider1000:inst2|clk_o divider2:inst1|oCLK selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { CLK selector:inst16|Pulse~26 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "29.000 ns" { CLK divider1000:inst2|clk_o divider2:inst1|oCLK selector:inst16|En~340 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { CLK selector:inst16|Pulse~26 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SIGNAL register counter:inst15\|cntbuf\[3\] register counter:inst15\|COUNT\[3\] 17.24 MHz 58.0 ns Internal " "Info: Clock SIGNAL has Internal fmax of 17.24 MHz between source register counter:inst15\|cntbuf\[3\] and destination register counter:inst15\|COUNT\[3\] (period= 58.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst15\|cntbuf\[3\] 1 REG LC1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'counter:inst15\|cntbuf\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { counter:inst15|cntbuf[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns counter:inst15\|COUNT\[3\] 2 REG LC7 9 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC7; Fanout = 9; REG Node = 'counter:inst15\|COUNT\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-45.000 ns - Smallest " "Info: - Smallest clock skew is -45.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SIGNAL destination 18.000 ns + Shortest register " "Info: + Shortest clock path from clock SIGNAL to destination register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SIGNAL 1 CLK PIN_22 18 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_22; Fanout = 18; CLK Node = 'SIGNAL'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { SIGNAL } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -24 -72 96 -8 "SIGNAL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns selector:inst16\|En~342 2 COMB SEXP1 12 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP1; Fanout = 12; COMB Node = 'selector:inst16\|En~342'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "10.000 ns" { SIGNAL selector:inst16|En~342 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns counter:inst15\|COUNT\[3\] 3 REG LC7 9 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC7; Fanout = 9; REG Node = 'counter:inst15\|COUNT\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "6.000 ns" { selector:inst16|En~342 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 88.89 % " "Info: Total cell delay = 16.000 ns ( 88.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 11.11 % " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "18.000 ns" { SIGNAL selector:inst16|En~342 counter:inst15|COUNT[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SIGNAL source 63.000 ns - Longest register " "Info: - Longest clock path from clock SIGNAL to source register is 63.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SIGNAL 1 CLK PIN_22 18 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_22; Fanout = 18; CLK Node = 'SIGNAL'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "" { SIGNAL } "NODE_NAME" } } } { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -24 -72 96 -8 "SIGNAL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns selector:inst16\|Pulse~25 2 COMB SEXP71 3 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP71; Fanout = 3; COMB Node = 'selector:inst16\|Pulse~25'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "10.000 ns" { SIGNAL selector:inst16|Pulse~25 } "NODE_NAME" } } } { "D:/051750/freqm/selector.vhd" "" "" { Text "D:/051750/freqm/selector.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 19.000 ns counter:inst10\|C 3 REG LC68 9 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC68; Fanout = 9; REG Node = 'counter:inst10\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "7.000 ns" { selector:inst16|Pulse~25 counter:inst10|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 28.000 ns counter:inst11\|C 4 REG LC66 9 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC66; Fanout = 9; REG Node = 'counter:inst11\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst10|C counter:inst11|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 37.000 ns counter:inst12\|C 5 REG LC100 9 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 37.000 ns; Loc. = LC100; Fanout = 9; REG Node = 'counter:inst12\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst11|C counter:inst12|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 46.000 ns counter:inst13\|C 6 REG LC98 9 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 46.000 ns; Loc. = LC98; Fanout = 9; REG Node = 'counter:inst13\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst12|C counter:inst13|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 55.000 ns counter:inst14\|C 7 REG LC55 8 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 55.000 ns; Loc. = LC55; Fanout = 8; REG Node = 'counter:inst14\|C'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "9.000 ns" { counter:inst13|C counter:inst14|C } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 63.000 ns counter:inst15\|cntbuf\[3\] 8 REG LC1 4 " "Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 63.000 ns; Loc. = LC1; Fanout = 4; REG Node = 'counter:inst15\|cntbuf\[3\]'" {  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "51.000 ns 80.95 % " "Info: Total cell delay = 51.000 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.000 ns 19.05 % " "Info: Total interconnect delay = 12.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { SIGNAL selector:inst16|Pulse~25 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "18.000 ns" { SIGNAL selector:inst16|En~342 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { SIGNAL selector:inst16|Pulse~25 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/counter.vhd" "" "" { Text "D:/051750/freqm/counter.vhd" 9 -1 0 } }  } 0}  } { { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "8.000 ns" { counter:inst15|cntbuf[3] counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "18.000 ns" { SIGNAL selector:inst16|En~342 counter:inst15|COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/db/freqm_cmp.qrpt" "" "" { Report "D:/051750/freqm/db/freqm_cmp.qrpt" Compiler "freqm" "UNKNOWN" "V1" "D:/051750/freqm/db/freqm.quartus_db" { Floorplan "" "" "63.000 ns" { SIGNAL selector:inst16|Pulse~25 counter:inst10|C counter:inst11|C counter:inst12|C counter:inst13|C counter:inst14|C counter:inst15|cntbuf[3] } "NODE_NAME" } } }  } 0}