freqm.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 15 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -152 -392 -224 -136 "CLK" "" } } } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SIGNAL " "Info: Assuming node SIGNAL is an undefined clock" {  } { { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -24 -72 96 -8 "SIGNAL" "" } } } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIGNAL" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SWITCH\[0\] " "Info: Assuming node SWITCH\[0\] is an undefined clock" {  } { { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -8 -72 96 8 "SWITCH\[1..0\]" "" } } } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SWITCH\[0\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SWITCH\[1\] " "Info: Assuming node SWITCH\[1\] is an undefined clock" {  } { { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { -8 -72 96 8 "SWITCH\[1..0\]" "" } } } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SWITCH\[1\]" } } } }  } 0}  } {  } 0}