selector.fit.eqn

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

--SIG2 is SIG2 at LC1
SIG2_reg_input = VCC;
SIG2 = TFFE(SIG2_reg_input, GLOBAL(SIG), , , );


--A1L6 is Pulse~9 at LC3
A1L6_p1_out = SW[0] & MCLK;
A1L6_p2_out = !SW[0] & SIG;
A1L6_or_out = A1L6_p1_out # A1L6_p2_out;
A1L6 = A1L6_or_out;


--A1L2 is En~100 at LC5
A1L2_p1_out = HCLK & !SW[0];
A1L2_p2_out = SW[0] & SIG2 & !SW[1];
A1L2_p3_out = SW[0] & SW[1] & SIG;
A1L2_or_out = A1L2_p1_out # A1L2_p2_out # A1L2_p3_out;
A1L2 = A1L2_or_out;


--MCLK is MCLK at PIN_81
--operation mode is input

MCLK = INPUT();


--HCLK is HCLK at PIN_33
--operation mode is input

HCLK = INPUT();


--SIG is SIG at PIN_83
--operation mode is input

SIG = INPUT();


--SW[1] is SW[1] at PIN_4
--operation mode is input

SW[1] = INPUT();


--SW[0] is SW[0] at PIN_52
--operation mode is input

SW[0] = INPUT();


--Pulse is Pulse at PIN_12
--operation mode is output

Pulse = OUTPUT(A1L6);


--En is En at PIN_11
--operation mode is output

En = OUTPUT(A1L2);