selector.tan.rpt

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+-------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To    ;
+-------+-------------------+-----------------+-------+-------+
; N/A   ; None              ; 15.000 ns       ; SW[0] ; En    ;
; N/A   ; None              ; 15.000 ns       ; HCLK  ; En    ;
; N/A   ; None              ; 15.000 ns       ; SW[1] ; En    ;
; N/A   ; None              ; 15.000 ns       ; SIG   ; En    ;
; N/A   ; None              ; 15.000 ns       ; SW[0] ; Pulse ;
; N/A   ; None              ; 15.000 ns       ; MCLK  ; Pulse ;
; N/A   ; None              ; 15.000 ns       ; SIG   ; Pulse ;
+-------+-------------------+-----------------+-------+-------+


+----------------------------------------------------------------------------+
; Minimum tco                                                                ;
+---------------+------------------+----------------+------+----+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+------+----+------------+
; N/A           ; None             ; 17.000 ns      ; SIG2 ; En ; SIG        ;
+---------------+------------------+----------------+------+----+------------+


+---------------------------------------------------------------------+
; Minimum tpd                                                         ;
+---------------+-------------------+-----------------+-------+-------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From  ; To    ;
+---------------+-------------------+-----------------+-------+-------+
; N/A           ; None              ; 15.000 ns       ; SIG   ; Pulse ;
; N/A           ; None              ; 15.000 ns       ; MCLK  ; Pulse ;
; N/A           ; None              ; 15.000 ns       ; SW[0] ; Pulse ;
; N/A           ; None              ; 15.000 ns       ; SIG   ; En    ;
; N/A           ; None              ; 15.000 ns       ; SW[1] ; En    ;
; N/A           ; None              ; 15.000 ns       ; HCLK  ; En    ;
; N/A           ; None              ; 15.000 ns       ; SW[0] ; En    ;
+---------------+-------------------+-----------------+-------+-------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Mon Dec 03 15:18:43 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off selector -c selector
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node SIG is an undefined clock
Info: Clock SIG has Internal fmax of 76.92 MHz between source register SIG2 and destination register SIG2 (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock SIG to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock SIG to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock SIG to destination pin En through register SIG2 is 17.000 ns
    Info: + Longest clock path from clock SIG to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'En~100'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'En'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Longest tpd from source pin SW[0] to destination pin En is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 5; PIN Node = 'SW[0]'
    Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'En~100'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'En'
    Info: Total cell delay = 13.000 ns ( 86.67 % )
    Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: Minimum tco from clock SIG to destination pin En through register SIG2 is 17.000 ns
    Info: + Shortest clock path from clock SIG to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'En~100'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'En'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Shortest tpd from source pin SIG to destination pin Pulse is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'Pulse~9'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'Pulse'
    Info: Total cell delay = 14.000 ns ( 93.33 % )
    Info: Total interconnect delay = 1.000 ns ( 6.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Dec 03 15:18:44 2007
    Info: Elapsed time: 00:00:00