freqm.tan.rpt

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------+-------------------------+------------+-----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                     ; To                      ; From Clock ; To Clock  ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------+-------------------------+------------+-----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; -3.000 ns                        ; SWITCH[0]                ; counter:inst10|C        ;            ; SWITCH[0] ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 55.000 ns                        ; counter:inst14|COUNT[3]  ; DIGSGN[0]               ; CLK        ;           ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 48.000 ns                        ; SIGNAL                   ; counter:inst14|C        ;            ; SWITCH[0] ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 26.000 ns                        ; dispselector:inst|POS[1] ; CATSEL[2]               ; CLK        ;           ; 0            ;
; Clock Setup: 'SWITCH[0]'     ; N/A                                      ; None          ; 17.24 MHz ( period = 58.000 ns ) ; counter:inst15|cntbuf[0] ; counter:inst15|COUNT[0] ; SWITCH[0]  ; SWITCH[0] ; 0            ;
; Clock Setup: 'SIGNAL'        ; N/A                                      ; None          ; 17.24 MHz ( period = 58.000 ns ) ; counter:inst15|cntbuf[0] ; counter:inst15|COUNT[0] ; SIGNAL     ; SIGNAL    ; 0            ;
; Clock Setup: 'CLK'           ; N/A                                      ; None          ; 21.28 MHz ( period = 47.000 ns ) ; counter:inst15|cntbuf[0] ; counter:inst15|COUNT[0] ; CLK        ; CLK       ; 0            ;
; Clock Hold: 'SIGNAL'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; selector:inst16|SIG2     ; counter:inst14|C        ; SIGNAL     ; SIGNAL    ; 9            ;
; Clock Hold: 'CLK'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; divider2:inst1|oCLK      ; counter:inst14|C        ; CLK        ; CLK       ; 9            ;
; Total number of failed paths ;                                          ;               ;                                  ;                          ;                         ;            ;           ; 18           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------+-------------------------+------------+-----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SIGNAL          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SWITCH[0]       ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SWITCH[1]       ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                             ; To                                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 21.28 MHz ( period = 47.000 ns )                    ; counter:inst15|cntbuf[3]                         ; counter:inst15|COUNT[3]                          ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 21.28 MHz ( period = 47.000 ns )                    ; counter:inst15|cntbuf[2]                         ; counter:inst15|COUNT[2]                          ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 21.28 MHz ( period = 47.000 ns )                    ; counter:inst15|cntbuf[1]                         ; counter:inst15|COUNT[1]                          ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 21.28 MHz ( period = 47.000 ns )                    ; counter:inst15|cntbuf[0]                         ; counter:inst15|COUNT[0]                          ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 26.32 MHz ( period = 38.000 ns )                    ; counter:inst14|cntbuf[3]                         ; counter:inst14|COUNT[3]                          ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 26.32 MHz ( period = 38.000 ns )                    ; counter:inst14|cntbuf[2]                         ; counter:inst14|COUNT[2]                          ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 26.32 MHz ( period = 38.000 ns )                    ; counter:inst14|cntbuf[1]                         ; counter:inst14|COUNT[1]                          ; CLK        ; CLK      ; None                        ; None                      ; None                    ;