divider.fit.eqn

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

--counter[0] is counter[0] at LC1
counter[0]_reg_input = VCC;
counter[0] = TFFE(counter[0]_reg_input, GLOBAL(iCLK), , , );


--counter[1] is counter[1] at LC2
counter[1]_or_out = counter[0];
counter[1]_reg_input = counter[1] $ counter[1]_or_out;
counter[1] = DFFE(counter[1]_reg_input, GLOBAL(iCLK), , , );


--counter[2] is counter[2] at LC4
counter[2]_p1_out = counter[8] & !counter[3] & counter[7] & counter[6] & counter[5] & counter[4] & counter[1] & counter[0];
counter[2]_p2_out = !counter[1] & !counter[2];
counter[2]_p3_out = !counter[0] & !counter[2];
counter[2]_p4_out = counter[1] & counter[0] & counter[2];
counter[2]_or_out = counter[2]_p1_out # counter[2]_p2_out # counter[2]_p3_out # counter[2]_p4_out;
counter[2]_reg_input = !(counter[2]_or_out);
counter[2] = DFFE(counter[2]_reg_input, GLOBAL(iCLK), , , );


--counter[3] is counter[3] at LC5
counter[3]_p1_out = counter[2] & counter[1] & counter[0];
counter[3]_or_out = counter[3];
counter[3]_reg_input = counter[3]_p1_out $ counter[3]_or_out;
counter[3] = DFFE(counter[3]_reg_input, GLOBAL(iCLK), , , );


--counter[4] is counter[4] at LC6
counter[4]_p1_out = counter[8] & counter[7] & counter[6] & counter[5] & !counter[3] & !counter[2] & counter[1] & counter[4] & counter[0];
counter[4]_p2_out = counter[3] & counter[2] & counter[1] & counter[0];
counter[4]_or_out = counter[4]_p1_out # counter[4]_p2_out;
counter[4]_reg_input = counter[4]_or_out;
counter[4] = TFFE(counter[4]_reg_input, GLOBAL(iCLK), , , );


--counter[5] is counter[5] at LC7
counter[5]_p1_out = counter[8] & counter[7] & counter[6] & !counter[3] & !counter[2] & counter[4] & counter[1] & counter[5] & counter[0];
counter[5]_p2_out = counter[3] & counter[2] & counter[4] & counter[1] & counter[0];
counter[5]_or_out = counter[5]_p1_out # counter[5]_p2_out;
counter[5]_reg_input = counter[5]_or_out;
counter[5] = TFFE(counter[5]_reg_input, GLOBAL(iCLK), , , );


--counter[6] is counter[6] at LC8
counter[6]_p1_out = counter[8] & counter[7] & !counter[3] & !counter[2] & counter[5] & counter[4] & counter[1] & counter[6] & counter[0];
counter[6]_p2_out = counter[3] & counter[2] & counter[5] & counter[4] & counter[1] & counter[0];
counter[6]_or_out = counter[6]_p1_out # counter[6]_p2_out;
counter[6]_reg_input = counter[6]_or_out;
counter[6] = TFFE(counter[6]_reg_input, GLOBAL(iCLK), , , );


--counter[7] is counter[7] at LC9
counter[7]_p1_out = counter[8] & !counter[3] & !counter[2] & counter[6] & counter[5] & counter[4] & counter[1] & counter[7] & counter[0];
counter[7]_p2_out = counter[3] & counter[2] & counter[6] & counter[5] & counter[4] & counter[1] & counter[0];
counter[7]_or_out = counter[7]_p1_out # counter[7]_p2_out;
counter[7]_reg_input = counter[7]_or_out;
counter[7] = TFFE(counter[7]_reg_input, GLOBAL(iCLK), , , );


--counter[8] is counter[8] at LC10
counter[8]_p1_out = counter[7] & counter[6] & counter[5] & counter[4] & !counter[3] & !counter[2] & counter[1] & counter[8] & counter[0];
counter[8]_p2_out = counter[7] & counter[6] & counter[5] & counter[4] & counter[3] & counter[2] & counter[1] & counter[0];
counter[8]_or_out = counter[8]_p1_out # counter[8]_p2_out;
counter[8]_reg_input = counter[8]_or_out;
counter[8] = TFFE(counter[8]_reg_input, GLOBAL(iCLK), , , );


--clk_o is clk_o at LC3
clk_o_p1_out = counter[8] & !counter[3] & !counter[2] & counter[7] & counter[6] & counter[5] & counter[4] & counter[1] & counter[0];
clk_o_or_out = clk_o_p1_out;
clk_o_reg_input = clk_o_or_out;
clk_o = TFFE(clk_o_reg_input, GLOBAL(iCLK), , , );


--iCLK is iCLK at PIN_83
--operation mode is input

iCLK = INPUT();


--oCLK is oCLK at PIN_12
--operation mode is output

oCLK = OUTPUT(clk_o);