📄 divider.tan.qmsg

📁 以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "iCLK register counter\[0\] register clk_o 76.92 MHz 13.0 ns Internal " "Info: Clock iCLK has Internal fmax of 76.92 MHz between source register counter\[0\] and destination register clk_o (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LC1 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 17; REG Node = 'counter\[0\]'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "" { counter[0] } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns clk_o 2 REG LC3 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "8.000 ns" { counter[0] clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "8.000 ns" { counter[0] clk_o } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock iCLK to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns iCLK 1 CLK PIN_83 10 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "" { iCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clk_o 2 REG LC3 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "0.000 ns" { iCLK clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK clk_o } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK source 3.000 ns - Longest register " "Info: - Longest clock path from clock iCLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns iCLK 1 CLK PIN_83 10 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "" { iCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns counter\[0\] 2 REG LC1 17 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 17; REG Node = 'counter\[0\]'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "0.000 ns" { iCLK counter[0] } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK counter[0] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK counter[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "8.000 ns" { counter[0] clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK counter[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "iCLK oCLK clk_o 8.000 ns register " "Info: tco from clock iCLK to destination pin oCLK through register clk_o is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK source 3.000 ns + Longest register " "Info: + Longest clock path from clock iCLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns iCLK 1 CLK PIN_83 10 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "" { iCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clk_o 2 REG LC3 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "0.000 ns" { iCLK clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK clk_o } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_o 1 REG LC3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "" { clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns oCLK 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'oCLK'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "4.000 ns" { clk_o oCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "4.000 ns" { clk_o oCLK } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "4.000 ns" { clk_o oCLK } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "iCLK oCLK clk_o 8.000 ns register " "Info: Minimum tco from clock iCLK to destination pin oCLK through register clk_o is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iCLK source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock iCLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns iCLK 1 CLK PIN_83 10 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "" { iCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clk_o 2 REG LC3 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "0.000 ns" { iCLK clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK clk_o } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_o 1 REG LC3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "" { clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns oCLK 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'oCLK'" {  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "4.000 ns" { clk_o oCLK } "NODE_NAME" } } } { "D:/051750/freqm/divider/divider.vhd" "" "" { Text "D:/051750/freqm/divider/divider.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "4.000 ns" { clk_o oCLK } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "3.000 ns" { iCLK clk_o } "NODE_NAME" } } } { "D:/051750/freqm/divider/db/divider_cmp.qrpt" "" "" { Report "D:/051750/freqm/divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "D:/051750/freqm/divider/db/divider.quartus_db" { Floorplan "" "" "4.000 ns" { clk_o oCLK } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 01 14:52:48 2008 " "Info: Processing ended: Tue Jan 01 14:52:48 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}
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