📄 divider.tan.rpt
字号:
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[4] ; counter[5] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[0] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[1] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[2] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[8] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[7] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[3] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[6] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[5] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[4] ; counter[6] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[0] ; counter[3] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[1] ; counter[3] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[2] ; counter[3] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[3] ; counter[3] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[0] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[1] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[2] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[8] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[7] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[3] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[6] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[5] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[4] ; counter[7] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[0] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[1] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[2] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[8] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[7] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[3] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[6] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[5] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[4] ; counter[8] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[0] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[1] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[2] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[8] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[7] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[3] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[6] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[5] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[4] ; counter[2] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[0] ; counter[1] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[1] ; counter[1] ; iCLK ; iCLK ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; counter[0] ; counter[0] ; iCLK ; iCLK ; None ; None ; None ;
+-------+----------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+------+------------+
; N/A ; None ; 8.000 ns ; clk_o ; oCLK ; iCLK ;
+-------+--------------+------------+-------+------+------------+
+-------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+-------+------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+-------+------+------------+
; N/A ; None ; 8.000 ns ; clk_o ; oCLK ; iCLK ;
+---------------+------------------+----------------+-------+------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue Jan 01 14:52:48 2008
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off divider -c divider
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node iCLK is an undefined clock
Info: Clock iCLK has Internal fmax of 76.92 MHz between source register counter[0] and destination register clk_o (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 17; REG Node = 'counter[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock iCLK to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock iCLK to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 17; REG Node = 'counter[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock iCLK to destination pin oCLK through register clk_o is 8.000 ns
Info: + Longest clock path from clock iCLK to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'oCLK'
Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Minimum tco from clock iCLK to destination pin oCLK through register clk_o is 8.000 ns
Info: + Shortest clock path from clock iCLK to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'iCLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Shortest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'clk_o'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'oCLK'
Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Tue Jan 01 14:52:48 2008
Info: Elapsed time: 00:00:00
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