dispselector.tan.qmsg

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DEBUG\[0\] POS\[0\] 20.000 ns register " "Info: tco from clock CLK to destination pin DEBUG\[0\] through register POS\[0\] is 20.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'CLK'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns POS\[0\] 2 REG LC7 60 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 60; REG Node = 'POS\[0\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "0.000 ns" { CLK POS[0] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "3.000 ns" { CLK POS[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest register pin " "Info: + Longest register to pin delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns POS\[0\] 1 REG LC7 60 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 60; REG Node = 'POS\[0\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "" { POS[0] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns DGT\[0\]~3358 2 COMB LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC8; Fanout = 1; COMB Node = 'DGT\[0\]~3358'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "8.000 ns" { POS[0] DGT[0]~3358 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns DGT\[0\]~3362 3 COMB LC9 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC9; Fanout = 1; COMB Node = 'DGT\[0\]~3362'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "1.000 ns" { DGT[0]~3358 DGT[0]~3362 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.000 ns DGT\[0\]~3368 4 COMB LC10 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC10; Fanout = 1; COMB Node = 'DGT\[0\]~3368'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "1.000 ns" { DGT[0]~3362 DGT[0]~3368 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 12.000 ns DGT\[0\]~3343 5 COMB LC11 1 " "Info: 5: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'DGT\[0\]~3343'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "2.000 ns" { DGT[0]~3368 DGT[0]~3343 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 16.000 ns DEBUG\[0\] 6 PIN PIN_8 0 " "Info: 6: + IC(0.000 ns) + CELL(4.000 ns) = 16.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'DEBUG\[0\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "4.000 ns" { DGT[0]~3343 DEBUG[0] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 87.50 % " "Info: Total cell delay = 14.000 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 12.50 % " "Info: Total interconnect delay = 2.000 ns ( 12.50 % )" {  } {  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "16.000 ns" { POS[0] DGT[0]~3358 DGT[0]~3362 DGT[0]~3368 DGT[0]~3343 DEBUG[0] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "3.000 ns" { CLK POS[0] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "16.000 ns" { POS[0] DGT[0]~3358 DGT[0]~3362 DGT[0]~3368 DGT[0]~3343 DEBUG[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "NUM5\[3\] DEBUG\[0\] 18.000 ns Longest " "Info: Longest tpd from source pin NUM5\[3\] to destination pin DEBUG\[0\] is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns NUM5\[3\] 1 PIN PIN_48 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_48; Fanout = 5; PIN Node = 'NUM5\[3\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "" { NUM5[3] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns DGT\[0\]~3358 2 COMB LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; COMB Node = 'DGT\[0\]~3358'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "8.000 ns" { NUM5[3] DGT[0]~3358 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns DGT\[0\]~3362 3 COMB LC9 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC9; Fanout = 1; COMB Node = 'DGT\[0\]~3362'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "1.000 ns" { DGT[0]~3358 DGT[0]~3362 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 12.000 ns DGT\[0\]~3368 4 COMB LC10 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 12.000 ns; Loc. = LC10; Fanout = 1; COMB Node = 'DGT\[0\]~3368'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "1.000 ns" { DGT[0]~3362 DGT[0]~3368 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 14.000 ns DGT\[0\]~3343 5 COMB LC11 1 " "Info: 5: + IC(0.000 ns) + CELL(2.000 ns) = 14.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'DGT\[0\]~3343'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "2.000 ns" { DGT[0]~3368 DGT[0]~3343 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 18.000 ns DEBUG\[0\] 6 PIN PIN_8 0 " "Info: 6: + IC(0.000 ns) + CELL(4.000 ns) = 18.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'DEBUG\[0\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "4.000 ns" { DGT[0]~3343 DEBUG[0] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 88.89 % " "Info: Total cell delay = 16.000 ns ( 88.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 11.11 % " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" {  } {  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "18.000 ns" { NUM5[3] DGT[0]~3358 DGT[0]~3362 DGT[0]~3368 DGT[0]~3343 DEBUG[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK CATSEL\[4\] POS\[2\] 17.000 ns register " "Info: Minimum tco from clock CLK to destination pin CATSEL\[4\] through register POS\[2\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'CLK'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns POS\[2\] 2 REG LC15 58 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC15; Fanout = 58; REG Node = 'POS\[2\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "0.000 ns" { CLK POS[2] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "3.000 ns" { CLK POS[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns POS\[2\] 1 REG LC15 58 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC15; Fanout = 58; REG Node = 'POS\[2\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "" { POS[2] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns Mux~295 2 COMB LC25 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC25; Fanout = 1; COMB Node = 'Mux~295'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "9.000 ns" { POS[2] Mux~295 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns CATSEL\[4\] 3 PIN PIN_17 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'CATSEL\[4\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "4.000 ns" { Mux~295 CATSEL[4] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "13.000 ns" { POS[2] Mux~295 CATSEL[4] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "3.000 ns" { CLK POS[2] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "13.000 ns" { POS[2] Mux~295 CATSEL[4] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "NUM4\[3\] DEBUG\[3\] 15.000 ns Shortest " "Info: Shortest tpd from source pin NUM4\[3\] to destination pin DEBUG\[3\] is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns NUM4\[3\] 1 PIN PIN_37 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_37; Fanout = 5; PIN Node = 'NUM4\[3\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "" { NUM4[3] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns DGT\[3\]~3337 2 COMB LC13 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC13; Fanout = 1; COMB Node = 'DGT\[3\]~3337'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "9.000 ns" { NUM4[3] DGT[3]~3337 } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns DEBUG\[3\] 3 PIN PIN_6 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'DEBUG\[3\]'" {  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "4.000 ns" { DGT[3]~3337 DEBUG[3] } "NODE_NAME" } } } { "D:/051750/freqm/dispselector/dispselector.vhd" "" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 86.67 % " "Info: Total cell delay = 13.000 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.33 % " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" {  } {  } 0}  } { { "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" "" "" { Report "D:/051750/freqm/dispselector/db/dispselector_cmp.qrpt" Compiler "dispselector" "UNKNOWN" "V1" "D:/051750/freqm/dispselector/db/dispselector.quartus_db" { Floorplan "" "" "15.000 ns" { NUM4[3] DGT[3]~3337 DEBUG[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 01 17:02:39 2008 " "Info: Processing ended: Tue Jan 01 17:02:39 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}