📄 dispselector.tan.rpt
字号:
; N/A ; None ; 15.000 ns ; NUM3[2] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM4[1] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM4[2] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM3[1] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM1[2] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM1[3] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM4[3] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM3[3] ; DEBUG[1] ;
; N/A ; None ; 15.000 ns ; NUM2[2] ; DEBUG[0] ;
; N/A ; None ; 15.000 ns ; NUM2[0] ; DEBUG[0] ;
; N/A ; None ; 15.000 ns ; NUM1[1] ; DEBUG[0] ;
; N/A ; None ; 15.000 ns ; NUM1[2] ; DEBUG[0] ;
; N/A ; None ; 15.000 ns ; NUM2[1] ; DEBUG[0] ;
; N/A ; None ; 15.000 ns ; NUM1[3] ; DEBUG[0] ;
; N/A ; None ; 15.000 ns ; NUM2[3] ; DEBUG[0] ;
; N/A ; None ; 16.000 ns ; NUM1[3] ; DEBUG[3] ;
; N/A ; None ; 16.000 ns ; NUM5[2] ; DEBUG[2] ;
; N/A ; None ; 16.000 ns ; NUM5[1] ; DEBUG[2] ;
; N/A ; None ; 16.000 ns ; NUM2[2] ; DEBUG[2] ;
; N/A ; None ; 16.000 ns ; NUM1[2] ; DEBUG[2] ;
; N/A ; None ; 16.000 ns ; NUM2[1] ; DEBUG[2] ;
; N/A ; None ; 16.000 ns ; NUM5[3] ; DEBUG[2] ;
; N/A ; None ; 16.000 ns ; NUM2[3] ; DEBUG[2] ;
; N/A ; None ; 16.000 ns ; NUM5[2] ; DEBUG[1] ;
; N/A ; None ; 16.000 ns ; NUM5[1] ; DEBUG[1] ;
; N/A ; None ; 16.000 ns ; NUM2[2] ; DEBUG[1] ;
; N/A ; None ; 16.000 ns ; NUM1[1] ; DEBUG[1] ;
; N/A ; None ; 16.000 ns ; NUM2[1] ; DEBUG[1] ;
; N/A ; None ; 16.000 ns ; NUM5[3] ; DEBUG[1] ;
; N/A ; None ; 16.000 ns ; NUM2[3] ; DEBUG[1] ;
; N/A ; None ; 16.000 ns ; NUM4[1] ; DEBUG[0] ;
; N/A ; None ; 16.000 ns ; NUM4[2] ; DEBUG[0] ;
; N/A ; None ; 16.000 ns ; NUM4[0] ; DEBUG[0] ;
; N/A ; None ; 16.000 ns ; NUM3[1] ; DEBUG[0] ;
; N/A ; None ; 16.000 ns ; NUM1[0] ; DEBUG[0] ;
; N/A ; None ; 16.000 ns ; NUM4[3] ; DEBUG[0] ;
; N/A ; None ; 16.000 ns ; NUM3[3] ; DEBUG[0] ;
; N/A ; None ; 17.000 ns ; NUM6[2] ; DEBUG[2] ;
; N/A ; None ; 17.000 ns ; NUM6[1] ; DEBUG[2] ;
; N/A ; None ; 17.000 ns ; NUM6[3] ; DEBUG[2] ;
; N/A ; None ; 17.000 ns ; NUM6[2] ; DEBUG[1] ;
; N/A ; None ; 17.000 ns ; NUM6[1] ; DEBUG[1] ;
; N/A ; None ; 17.000 ns ; NUM6[3] ; DEBUG[1] ;
; N/A ; None ; 17.000 ns ; NUM3[0] ; DEBUG[0] ;
; N/A ; None ; 17.000 ns ; NUM6[2] ; DEBUG[0] ;
; N/A ; None ; 17.000 ns ; NUM6[1] ; DEBUG[0] ;
; N/A ; None ; 17.000 ns ; NUM6[0] ; DEBUG[0] ;
; N/A ; None ; 17.000 ns ; NUM3[2] ; DEBUG[0] ;
; N/A ; None ; 17.000 ns ; NUM6[3] ; DEBUG[0] ;
; N/A ; None ; 18.000 ns ; NUM5[2] ; DEBUG[0] ;
; N/A ; None ; 18.000 ns ; NUM5[1] ; DEBUG[0] ;
; N/A ; None ; 18.000 ns ; NUM5[0] ; DEBUG[0] ;
; N/A ; None ; 18.000 ns ; NUM5[3] ; DEBUG[0] ;
+---------------+-------------------+-----------------+---------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue Jan 01 17:02:39 2008
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off dispselector -c dispselector
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
Info: Clock CLK has Internal fmax of 76.92 MHz between source register POS[0] and destination register POS[2] (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 60; REG Node = 'POS[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC15; Fanout = 58; REG Node = 'POS[2]'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock CLK to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'CLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC15; Fanout = 58; REG Node = 'POS[2]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock CLK to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'CLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 60; REG Node = 'POS[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock CLK to destination pin DEBUG[0] through register POS[0] is 20.000 ns
Info: + Longest clock path from clock CLK to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'CLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 60; REG Node = 'POS[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 16.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 60; REG Node = 'POS[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC8; Fanout = 1; COMB Node = 'DGT[0]~3358'
Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC9; Fanout = 1; COMB Node = 'DGT[0]~3362'
Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC10; Fanout = 1; COMB Node = 'DGT[0]~3368'
Info: 5: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'DGT[0]~3343'
Info: 6: + IC(0.000 ns) + CELL(4.000 ns) = 16.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'DEBUG[0]'
Info: Total cell delay = 14.000 ns ( 87.50 % )
Info: Total interconnect delay = 2.000 ns ( 12.50 % )
Info: Longest tpd from source pin NUM5[3] to destination pin DEBUG[0] is 18.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_48; Fanout = 5; PIN Node = 'NUM5[3]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; COMB Node = 'DGT[0]~3358'
Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC9; Fanout = 1; COMB Node = 'DGT[0]~3362'
Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 12.000 ns; Loc. = LC10; Fanout = 1; COMB Node = 'DGT[0]~3368'
Info: 5: + IC(0.000 ns) + CELL(2.000 ns) = 14.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'DGT[0]~3343'
Info: 6: + IC(0.000 ns) + CELL(4.000 ns) = 18.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'DEBUG[0]'
Info: Total cell delay = 16.000 ns ( 88.89 % )
Info: Total interconnect delay = 2.000 ns ( 11.11 % )
Info: Minimum tco from clock CLK to destination pin CATSEL[4] through register POS[2] is 17.000 ns
Info: + Shortest clock path from clock CLK to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'CLK'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC15; Fanout = 58; REG Node = 'POS[2]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Shortest register to pin delay is 13.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC15; Fanout = 58; REG Node = 'POS[2]'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC25; Fanout = 1; COMB Node = 'Mux~295'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'CATSEL[4]'
Info: Total cell delay = 11.000 ns ( 84.62 % )
Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Shortest tpd from source pin NUM4[3] to destination pin DEBUG[3] is 15.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_37; Fanout = 5; PIN Node = 'NUM4[3]'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC13; Fanout = 1; COMB Node = 'DGT[3]~3337'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'DEBUG[3]'
Info: Total cell delay = 13.000 ns ( 86.67 % )
Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Tue Jan 01 17:02:39 2008
Info: Elapsed time: 00:00:00
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