divclk.vhd

来自「SOPC Builder创建的CPU」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DivClk is
    port(clk:in std_logic;
        divclk:out std_logic);
end DivClk;
architecture Behavioral of DivClk is
signal count:std_logic_vector(4 downto 0):="00000";
signal tempdivclk:std_logic:='0';
begin
    process(clk)
    begin
        if clk'event and clk='1' then
            if(count<="11000") then
                count<="00000";
                tempdivclk<=not tempdivclk;
            else
               count<=count+'1'; 
            end if;
            
        end if;
    end process;
    divclk<=tempdivclk;
end Behavioral;