t_add_half.v

来自「SOPC Builder创建的CPU」· Verilog 代码 · 共 18 行

module t_Add_half();
	wire  sum,c_out;
	reg   a,b;
	Add_half_0_delay M1 (sum,c_out,a,b);
	
	initial begin
	#100 $finish;
	end
	
	initial begin
	#10 a=0;b=0;
	#10 b=1;
	#10 a=1;
	#10 b=0;
	end 
	endmodule