aoi_5_ca0.v

来自「SOPC Builder创建的CPU」· Verilog 代码 · 共 5 行

module AOI_5_CA0(y_out,x_in1,x_in2,x_in3,x_in4,x_in5,enable);
	input x_in1,x_in2,x_in3,x_in4,x_in5,enable;
	output y_out;
	wire y_out=enable?~((x_in1&x_in2)|(x_in3&x_in4&x_in5)):1'bz;
	endmodule