aoi_5_ca3.v

来自「SOPC Builder创建的CPU」· Verilog 代码 · 共 8 行

module AOI_5_CA3(y_out,x_in1,x_in2,x_in3,x_in4);
   input x_in1,x_in2,x_in3,x_in4;
   output y_out;
   wire #1 y1=x_in1&x_in2;
   wire #1 y2=x_in3&x_in4;
   wire #1 y_out=~(y1|y2);
   endmodule