add_full_0_delay.v

来自「SOPC Builder创建的CPU」· Verilog 代码 · 共 11 行

module Add_full_0_delay(sum,c_out,a,b,c_in);
    input a,b,c_in;
    output sum,c_out;
    wire w1,w2,w3;
    
    Add_half_0_delay M1 (w1,w2,a,b);
    Add_half_0_delay M2 (sum,c_out,c_in,w1);
    or(c_out,w3,w2);
endmodule