📄 add2in.vhd
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity Add2In is port(D1:in std_logic_vector(7 downto 0); D2:in std_logic_vector(7 downto 0); Q: out std_logic_vector(8 downto 0); clk:in std_logic);end Add2In;architecture behavior of Add2In is begin process(clk) begin if clk'event and clk='1' then Q<=(D1(D1'left)&D1)+(D2(D2'left)&D2); end if; end process; end behavior;
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