_primary.vhd

来自「SOPC Builder创建的CPU」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity Add_half_0_delay is
    port(
        sum             : out    vl_logic;
        c_out           : out    vl_logic;
        a               : in     vl_logic;
        b               : in     vl_logic
    );
end Add_half_0_delay;