gt.vhd

last cordic for immplemantaion of cordic with vhdl language it has testbench

 -- Description : single bit generate and propigate signals for CLA

library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;

entity gt is port (
 x : in std_logic;
 y : in std_logic;
 g : out std_logic;
 t : out std_logic);
end gt;

architecture behavioral of gt is

begin

 g <= (x and y);

 t <= (x or y) ;
end behavioral;