cla16.vhd

来自「last cordic for immplemantaion of cordic」· VHDL 代码 · 共 51 行

 -- Description : 16 bit CLA
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;

entity cla16 is port (
 x : in std_logic_vector(15 downto 0);
 y : in std_logic_vector(15 downto 0);
 c_in : in std_logic;
 z : out std_logic_vector(15 downto 0));
end cla16;

architecture behavioral of cla16 is

 component cla4 is port (
 x : in std_logic_vector(3 downto 0);
 y : in std_logic_vector(3 downto 0);
 c_in : in std_logic;
 z : out std_logic_vector(3 downto 0)); --sum out
 end component;

 signal c : std_logic_vector(3 downto 0);
 signal g : std_logic_vector(3 downto 0);
 signal t : std_logic_vector(3 downto 0);

 begin

 cla4_0 : cla4 port map(x( 3 downto 0), y( 3 downto 0), c(0), z( 3 downto 0), t(0), g(0));
 cla4_1 : cla4 port map(x( 7 downto 4), y( 7 downto 4), c(1), z( 7 downto 4), t(1), g(1));
 cla4_2 : cla4 port map(x(11 downto 8), y(11 downto 8), c(2), z(11 downto 8), t(2), g(2));
 cla4_3 : cla4 port map(x(15 downto 12), y(15 downto 12), c(3), z(15 downto 12), t(3), g(3));

 c(0) <= c_in;

 c(1) <= (g(0) ) or
 (c_in and t(0)) ;

 c(2) <= (g(1) ) or
 (g(0) and t(1) ) or
 (c_in and t(1) and t(0));

 c(3) <= (g(2) ) or
 (g(1) and t(2) ) or
 (g(0) and t(2) and t(1) ) or
 (c_in and t(2) and t(1) and t(0)) ;


 end behavioral;