state.vhd

last cordic for immplemantaion of cordic with vhdl language it has testbench

-- Description : state counter for time iterative CORDIC
library ieee;
library work;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use work.all;

 entity state is port(
 clock : in std_logic;
 go : in std_logic;
 ready : out std_logic;
 counter : out integer range 0 to 63);
 end state;

 architecture behavioral of state is

 --state signal
 signal count : integer range 0 to 63;

 begin
 process(clock)
 begin
 if rising_edge(clock) then
 if (go = '1') then
 count <= 0;
 elsif (count = 63) then
 count <= count;
 else
 count <= count+1;
 end if;
 end if;
 end process;
 counter <= count;

 ready <= '1' when count = 63 else '0';

 end behavioral;