cla4.vhd

last cordic for immplemantaion of cordic with vhdl language it has testbench

 -- Description : 4 bit CLA

library IEEE;
library work;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use work.all;

 entity cla4 is port (
 x : in std_logic_vector(3 downto 0);
 y : in std_logic_vector(3 downto 0);
 c_in : in std_logic;
 z : out std_logic_vector(3 downto 0)); --sum out
 end cla4;

 architecture behavioral of cla4 is

component gt is port (
 x : in std_logic;
 y : in std_logic;
 g : out std_logic;
 t : out std_logic);
 end component;


 component add is port (
 c : in std_logic;
 t : in std_logic;
 g : in std_logic;
 z : out std_logic);
 end component;

 signal c : std_logic_vector(3 downto 0);
 signal g : std_logic_vector(3 downto 0);
 signal t : std_logic_vector(3 downto 0);

 begin

 block0 : gt port map(x(0), y(0), g(0), t(0));
 block1 : gt port map(x(1), y(1), g(1), t(1));
 block2 : gt port map(x(2), y(2), g(2), t(2));
 block3 : gt port map(x(3), y(3), g(3), t(3));

 c(0) <= c_in;

 c(1) <= (g(0) ) or
 (c_in and t(0)) ;

 c(2) <= (g(1) ) or
 (g(0) and t(1) ) or
 (c_in and t(1) and t(0)) ;

 c(3) <= (g(2) ) or
 (g(1) and t(2) ) or
 (g(0) and t(2) and t(1) ) or
 (c_in and t(2) and t(1) and t(0)) ;

 add0 : add port map(c(0), t(0), g(0), z(0));
 add1 : add port map(c(1), t(1), g(1), z(1));
 add2 : add port map(c(2), t(2), g(2), z(2));
 add3 : add port map(c(3), t(3), g(3), z(3));

 end behavioral;