cla64.vhd

last cordic for immplemantaion of cordic with vhdl language it has testbench

 -- Description : 64 bit CLA
library IEEE;
library work;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use work.all;

entity cla64 is port (
 x : in std_logic_vector(63 downto 0);
 y : in std_logic_vector(63 downto 0);
 c_in : in std_logic;
 z : out std_logic_vector(63 downto 0));
end cla64;

architecture behavioral of cla64 is

component cla16 is port (
 x : in std_logic_vector(15 downto 0);
 y : in std_logic_vector(15 downto 0);
 c_in : in std_logic;
 z : out std_logic_vector(15 downto 0));
end component;

signal c : std_logic_vector(3 downto 0);
signal g : std_logic_vector(3 downto 0);
signal t : std_logic_vector(3 downto 0);

 begin

 cla16_0 : cla16 port map(x(15 downto 0), y(15 downto 0), c(0), z(15 downto 0), t(0), g(0));
 cla16_1 : cla16 port map(x(31 downto 16), y(31 downto 16), c(1), z(31 downto 16), t(1), g(1));
 cla16_2 : cla16 port map(x(47 downto 32), y(47 downto 32), c(2), z(47 downto 32), t(2), g(2));
 cla16_3 : cla16 port map(x(63 downto 48), y(63 downto 48), c(3), z(63 downto 48), t(3), g(3));

c(0) <= c_in;

c(1) <= (g(0) ) or
(c_in and t(0)) ;

c(2) <= (g(1) ) or
(g(0) and t(1) ) or
(c_in and t(1) and t(0)) ;

c(3) <= (g(2) ) or
(g(1) and t(2) ) or
(g(0) and t(2) and t(1) ) or
(c_in and t(2) and t(1) and t(0)) ;

 end behavioral;