reg.vhd

last cordic for immplemantaion of cordic with vhdl language it has testbench

-- Description : 64 bit register and input mux

library ieee;
library work;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use work.all;
 entity reg is port(
 clock : in std_logic;
 go : in std_logic;
 d : in std_logic_vector(63 downto 0);
 add : in std_logic_vector(63 downto 0);
 latch : out std_logic_vector(63 downto 0));
 end reg;

 architecture behavioral of reg is

 begin

 process(clock)
 begin
 if rising_edge(clock) then
 if (go = '1') then

 latch <=d;
 else

 latch <= add ;
 end if;
 end if;
 end process;

 end behavioral;