addsub64.vhd

last cordic for immplemantaion of cordic with vhdl language it has testbench

 -- Description : 64 bit  adder/subtractor

library ieee;
library work;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use work.all;
 entity addsub64 is port(
   x : in std_logic_vector(63 downto 0);
   y : in std_logic_vector(63 downto 0);
   mode : in std_logic; --add when '0', sub when '1'
   z : out std_logic_vector(63 downto 0));
 end addsub64;

 architecture behavioral of addsub64 is
 
 component cla64 is port(
 x : in std_logic_vector(63 downto 0);
y : in std_logic_vector(63 downto 0);
c_in : in std_logic;
z : out std_logic_vector(63 downto 0));
end component;

 signal z_temp:std_logic_vector(63 downto 0);
 signal x_0:std_logic_vector(63 downto 0);
 signal x_1:std_logic_vector(63 downto 0);
 signal y_0:std_logic_vector(63 downto 0);
 signal y_1:std_logic_vector(63 downto 0);
 signal c_0:std_logic;

 begin
  x_0<=(others=>'0');
 x_1<=(0 =>'1', others =>'0');
 y_0<=(others=>'0');
 y_1<= not y;
 c_0<='0';
 process(y, mode)
 begin

 if (mode = '0') then -- add, +y

    add64_0: cla64 port map (x_0,y,c_0,z_temp);
   -- z_temp=y
 elsif (mode = '1') then -- sub, -y+1
    add64_1: cla64 port map (x_1,y_1,c_0,z_temp);
--    z_temp=-y+1
 end if;
 
 end process;

 add : cla64 port map (x,z_temp,c_in,z);

 end behavioral;