cordic.vhd

last cordic for immplemantaion of cordic with vhdl language it has testbench

-- Description : root CORDIC source
library ieee;
library work;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use work.all;

 entity cordic is port(
 clock : in std_logic;
 go : in std_logic;
 x : in std_logic_vector(63 downto 0);
 y : in std_logic_vector(63 downto 0);
 z : in std_logic_vector(63 downto 0);
 ready : out std_logic;
 x_out : out std_logic_vector(63 downto 0);
 y_out : out std_logic_vector(63 downto 0);
 z_out : out std_logic_vector(63 downto 0));
 end cordic;

 architecture behavioral of cordic is

 component Reg is port(
 clock : in std_logic;
 go : in std_logic;
 d : in std_logic_vector(63 downto 0);
 add : in std_logic_vector(63 downto 0);
 latch : out std_logic_vector(63 downto 0));
end component;

 component addsub64 is port(
 x : in std_logic_vector(63 downto 0);
 y : in std_logic_vector(63 downto 0);
 mode : in std_logic; --add when '0', sub when '1'
 z : out std_logic_vector(63 downto 0));
 end component;

-- component bsd2cla64 is port(
 --x : in std_logic_vector(63 downto 0);
 --x_out : out std_logic_vector(63 downto 0));
 --end component;

 component xsign is port(
 x : in std_logic_vector(63 downto 0);
 d : out std_logic); --'1' when neg, else '0'
 end component;

 component shifter is port (
 x : in std_logic_vector(63 downto 0);
 i : in integer range 0 to 63; --number of bits to right shift
 shift : out std_logic_vector(63 downto 0));
 end component;

 component state is port(
 clock : in std_logic;
 go : in std_logic;
 ready : out std_logic;
 counter : out integer range 0 to 63);
 end component;

 component lut is port (
 i : in integer range 0 to 63;
 lut_out : out std_logic_vector(63 downto 0));
 end component;

 --net names
 signal counter : integer range 0 to 63;
 signal x_reg : std_logic_vector(63 downto 0);
 signal y_reg : std_logic_vector(63 downto 0);
 signal z_reg : std_logic_vector(63 downto 0);
 signal x_shift : std_logic_vector(63 downto 0);
 signal y_shift : std_logic_vector(63 downto 0);
 signal d : std_logic;
 signal not_d : std_logic;
 signal x_add : std_logic_vector(63 downto 0);
 signal y_add : std_logic_vector(63 downto 0);
 signal z_add : std_logic_vector(63 downto 0);
 signal lut_out : std_logic_vector(63 downto 0);

 begin
 not_d <= not d;

 --adders
 add_x : addsub64 port map(x_reg, y_shift, not_d, x_add);
 add_y : addsub64 port map(y_reg, x_shift, d, y_add);
 add_z : addsub64 port map(z_reg, lut_out, not_d, z_add);

 --shifters
 shift_x : shifter port map(x_reg, counter, x_shift);
 shify_y : shifter port map(y_reg, counter, y_shift);

 --sign detection
 sign : xsign port map(z_reg, d);

 --look up table
 lut1 : lut port map(counter, lut_out);

 --state machine
 cnt : state port map(clock, go, ready, counter);

--register mux
 xreg : Reg port map(clock, go, x, x_add, x_reg);
 yreg : Reg port map(clock, go, y, y_add, y_reg);
 zreg : Reg port map(clock, go, z, z_add, z_reg);

 --ouput CLAs
 --cla_x : bsd2cla64 port map(x_reg, x_out);
 --cla_y : bsd2cla64 port map(y_reg, y_out);
 --cla_z : bsd2cla64 port map(z_out, z_out);
 x_out<=x_reg;
 y_out<=y_reg;
 z_out<=z_out;
 end behavioral;