clock.v

来自「ARM7 verilog vhdl code」· Verilog 代码 · 共 20 行

`define TIME_LIMIT 110000

module c1(clk);
   output clk;
   reg clk;

   always 
      begin
         if ($time == 0) 
            begin 
               clk = 0; 
            end
         #50 clk = ~clk;
      end

   always @(posedge clk)
      if ($time > `TIME_LIMIT) 
         #70 $stop;
endmodule