prev_cmp_encoder.tan.qmsg

一个简单的VHDL3-8译码程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 13 10:43:58 2008 " "Info: Processing started: Sat Dec 13 10:43:58 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off encoder -c encoder " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off encoder -c encoder" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "input\[7\] y\[1\] 10.000 ns Longest " "Info: Longest tpd from source pin \"input\[7\]\" to destination pin \"y\[1\]\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns input\[7\] 1 PIN PIN_37 3 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_37; Fanout = 3; PIN Node = 'input\[7\]'" {  } { { "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { input[7] } "NODE_NAME" } } { "encoder.vhd" "" { Text "D:/启航VHDL/3-8译码/encoder.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 8.400 ns Mux1~12 2 COMB LC6 1 " "Info: 2: + IC(3.200 ns) + CELL(4.000 ns) = 8.400 ns; Loc. = LC6; Fanout = 1; COMB Node = 'Mux1~12'" {  } { { "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { input[7] Mux1~12 } "NODE_NAME" } } { "encoder.vhd" "" { Text "D:/启航VHDL/3-8译码/encoder.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.000 ns y\[1\] 3 PIN PIN_143 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'y\[1\]'" {  } { { "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { Mux1~12 y[1] } "NODE_NAME" } } { "encoder.vhd" "" { Text "D:/启航VHDL/3-8译码/encoder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.800 ns ( 68.00 % ) " "Info: Total cell delay = 6.800 ns ( 68.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 32.00 % ) " "Info: Total interconnect delay = 3.200 ns ( 32.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { input[7] Mux1~12 y[1] } "NODE_NAME" } } { "d:/quartus2/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus2/altera/72/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { input[7] {} input[7]~out {} Mux1~12 {} y[1] {} } { 0.000ns 0.000ns 3.200ns 0.000ns } { 0.000ns 1.200ns 4.000ns 1.600ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 13 10:44:00 2008 " "Info: Processing ended: Sat Dec 13 10:44:00 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}