encoder.vhd

一个简单的VHDL3-8译码程序

library ieee;
use ieee.std_logic_1164.all;
entity encoder is
	port(input:in std_logic_vector(7 downto 0);
			y:out std_logic_vector(2 downto 0));
end encoder;

architecture rt1 of encoder is
begin 
	process(input)
		begin
			case input is
				when"01111111"=>y<="000";
				when"10111111"=>y<="001";
				when"11011111"=>y<="010";
				when"11101111"=>y<="011";
				when"11110111"=>y<="100";
				when"11111011"=>y<="101";
				when"11111101"=>y<="110";
				when"11111110"=>y<="111";
				when others=>y<="XXX";
			end case;
	end process;
end rt1;